Capacitively-coupled stacked class-D oscillators for galvanic isolation

A device comprising:

• a first oscillator circuit;
• a second oscillator circuit concatenated with the first oscillator circuit, wherein the first oscillator circuit and the second oscillator circuit are configured to be coupled between a supply voltage and an electrical ground, wherein each of the first oscillator circuit and the second oscillator circuit is a class-D oscillator circuit, wherein the class-D oscillator circuit comprises:
• a first transistor coupled between a reference voltage node of the class-D oscillator circuit and a first output of the class-D oscillator circuit;
• a second transistor coupled between the reference voltage node of the class-D oscillator circuit and a second output of the class-D oscillator circuit, wherein a gate terminal of the first transistor and a gate terminal of the second transistor are coupled to a bias voltage node of the class-D oscillator circuit;
• and
• an LC tank circuit comprising:
• a first capacitor coupled between the first output and the second output of the class-D oscillator circuit;
• and
• a first coil coupled in parallel with the first capacitor;
• and
• a second capacitor coupled between the first output of the first oscillator circuit and the first output of the second oscillator circuit;
• and
• a third capacitor coupled between the second output of the first oscillator circuit and the second output of the second oscillator circuit, wherein the bias voltage node of the first oscillator circuit is configured to be supplied with a first bias voltage, wherein the bias voltage node of the second oscillator circuit is configured to be supplied with a second bias voltage higher than the first bias voltage.

An integrated circuit (IC) device comprising:

• a first oscillator circuit comprising:
• a first transistor and a second transistor, wherein gate terminals of the first transistor and the second transistor are coupled to a first node;
• a first coil coupled between a drain terminal of the first transistor and a drain terminal of the second transistor;
• and
• a first capacitor coupled in parallel with the first coil;
• a second oscillator circuit, wherein the second oscillator circuit has an identical structure as the first oscillator circuit, wherein a source terminal of the first transistor of the first oscillator circuit and a source terminal of the second transistor of the first oscillator circuit are coupled to a reference voltage node, wherein a source terminal of the first transistor of the second oscillator circuit and a source terminal of the second transistor of the second oscillator circuit are coupled to a center tap of the first coil of the first oscillator circuit, wherein a center tap of the first coil of the second oscillator circuit is coupled to a supply voltage node, wherein the first node of the first oscillator circuit is configured to be supplied with a first bias voltage, and the first node of the second oscillator circuit is configured to be supplied with a second bias voltage different from the first bias voltage;
• a second capacitor coupled between the drain terminal of the first transistor of the first oscillator circuit and the drain terminal of the first transistor of the second oscillator circuit;
• and
• a third capacitor coupled between the drain terminal of the second transistor of the first oscillator circuit and the drain terminal of the second transistor of the second oscillator circuit.