US 11,901,803 B2Granted

Pass gate driver

AssigneeTexas Instruments Incorporated

InventorsBernhard Wolfgang Ruck, Ruediger Kuhn, Oliver Nehrig

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Abstract

A driver includes a low-resistance charging path between a supply voltage rail and a first output node, a high-resistance charging path between the supply voltage rail and the first output node, an inverter coupled to the first output node and configured to enable and disable the low-resistance charging path, and a high-resistance discharging path between the first output node and a second output node. The first output node is coupled to a control terminal of a pass gate transistor in some implementations. The low-resistance charging path charges a voltage on the first output node to a threshold voltage of the pass gate transistor, and the high-resistance charging path charges the voltage on the first output node greater than the threshold voltage of the pass gate transistor. The high-resistance discharging path discharges the voltage on the first output node.

Claims16

Dependent claims

A driver circuit, comprising:

a first transistor having a first control terminal coupled to an input node, a first current terminal coupled to a supply voltage rail, and a second current terminal;
a second transistor having a second control terminal configured to receive a first biasing voltage, a third current terminal coupled to the second current terminal, and a fourth current terminal coupled to a first output node;
a third transistor having a third control terminal configured to receive a second biasing voltage, a fifth current terminal coupled to the first output node, a sixth current terminal;
a fourth transistor having a fourth control terminal coupled to the input node, a seventh current terminal coupled to the sixth current terminal, and an eighth current terminal coupled to a second output node;
a fifth transistor having a fifth control terminal, a ninth current terminal coupled to the second and third current terminals, and a tenth current terminal;
a sixth transistor having a sixth control terminal configured to receive the first biasing voltage, an eleventh current terminal coupled to the tenth current terminal, and a twelfth current terminal coupled to the first output node;
a first inverter, comprising:
a seventh transistor having a seventh control terminal coupled to the first output node, a thirteenth current terminal coupled to the supply voltage rail, and a fourteenth current terminal;
and
an eighth transistor having an eighth control terminal coupled to the first output node, a fifteenth current terminal coupled to the fourteenth current terminal, and a sixteenth current terminal coupled to the second output node;
and
a second inverter having an input coupled to the fourteenth and fifteenth current terminals and an output coupled to the fifth control terminal.

9 more elements

A circuit, comprising:

a first transistor coupled to a supply voltage rail and having a first control terminal coupled to an input node;
a second transistor coupled between the first transistor and a first output node, the second transistor having a second control terminal configured to receive a first biasing voltage;
a third transistor coupled to the first output node and having a third control terminal configured to receive a second biasing voltage;
a fourth transistor coupled between the third transistor and a second output node, the fourth transistor having a fourth control terminal coupled to the input node;
a fifth transistor coupled to the first and second transistors and having a fifth control terminal;
a sixth transistor coupled between the fifth transistor and the first output node, the sixth transistor having a sixth control terminal configured to receive the first biasing voltage;
a first inverter, comprising:
a seventh transistor coupled to the supply voltage rail and having a seventh control terminal coupled to the first output node;
and
an eighth transistor coupled between the seventh transistor and the second output node, the eighth transistor having an eighth control terminal coupled to the first output node;
and
a second inverter coupled to the seventh and eighth transistors and to the fifth control terminal.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/560,756Filed 23 Dec 2021
Published: US 2023/0208291 A129 Jun 2023
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G05F 1/59
Using semiconductor devices in series with the load as final control devices: including plural semiconductor devices as final control devices for…
H02M 1/08
Details of apparatus for conversion: circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in…
G05F 1/46
Regulating voltage or current: wherein the variable actually regulated by the final control device is DC
G05F 1/575
Using semiconductor devices in series with the load as final control devices: characterised by the feedback circuit