Apparatuses and method for over-voltage event protection
AssigneeMicron Technology, Inc.
InventorsJames Davis, Michael Chaine
Life of this patent
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Abstract
Circuits, integrated circuits, apparatuses, and methods, such as those for protecting circuits against electrostatic discharge events are disclosed. An example apparatus comprises a thyristor coupled to a node and configured to limit the voltage and discharge the current associated with an over-voltage event at the node. The over-voltage event includes a negative voltage having a magnitude that exceeds a trigger voltage of the thyristor. The example apparatus further comprising a transistor coupled to the thyristor and configured to adjust the magnitude of the trigger voltage.
Claims12
An apparatus comprising:
- a bulk material doped with a first dopant type, wherein the bulk material includes a first well doped with a second dopant type, wherein the first well includes a first region, a second region, and a second well doped with the second dopant type, wherein the second well includes a third region doped with the first dopant type, wherein the third region, the second well, the first well, and the second region together form a thyristor, wherein the first region and the first well are coupled to a reference node, wherein the third region is coupled to a pad configured to provide an input signal;
- and
- a gate formed on a surface of the bulk material overlapping an area between the first region and the second region, wherein the gate is coupled to a trigger voltage source configured to set the trigger voltage of the thyristor.
An apparatus comprising:
- a first well formed with a first dopant type, wherein the first well includes a first region, a second region, and a second well doped with a second dopant type, wherein the second well includes a third region doped with the second dopant type, wherein the third region, the second well, the first well, and the second region together form a thyristor, wherein the first region and the first well are coupled to a reference node, wherein the third region is coupled to a pad configured to provide an input signal;
- and
- a gate overlapping an area between the first region and the second region, wherein the gate is coupled to a trigger voltage source configured to set the trigger voltage of the thyristor.
Dependencies are inferred from the claim text.