Contaminant collection on SOI
AssigneeTexas Instruments Incorporated
InventorsHonglin Guo, Zachary K Lee, Jingjing Chen
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.
Claims37
An integrated circuit comprising:
- a semiconductor-on-insulator (SOI) substrate having a semiconductor layer over a buried insulator layer, the semiconductor layer including white space regions that include a P-type well (PWELL) region;
- an electronic device that includes an N-type well (NWELL) region formed in the semiconductor layer, a dielectric formed over the NWELL region, and a polysilicon plate over the dielectric;
- and
- a sacrificial NWELL ring adjacent to and separated from the NWELL region by a first gap.
A method of fabricating an integrated circuit, the method comprising:
- providing a semiconductor-on-insulator (SOI) substrate that includes a buried insulator layer;
- forming an N-type well (NWELL) region and a sacrificial NWELL ring in a semiconductor layer of the SOI substrate, the sacrificial NWELL ring at a first side of the NWELL region and separated from the NWELL region by a first gap;
- forming a P-type well (PWELL) region in a white space region of the semiconductor layer at the first side of the NWELL region;
- forming a dielectric over the NWELL region;
- and
- forming a polysilicon plate over the dielectric.
An integrated circuit comprising:
- a semiconductor-on-insulator (SOI) substrate having a silicon layer over a buried oxide layer, the silicon layer including white space regions that include a P-type well (PWELL) region;
- a capacitor that includes an N-type well (NWELL) region formed in the silicon layer, an oxide formed over the NWELL region, and a polysilicon plate formed over the oxide;
- a first sacrificial NWELL ring adjacent to and separated from the NWELL region by a first gap;
- and
- a second sacrificial NWELL ring adjacent to and separated from the first sacrificial NWELL ring by a second gap.
A semiconductor device, comprising:
- a semiconductor-on-insulator (SOI) substrate including a semiconductor layer over a buried insulator layer;
- an N-type well (NWELL) region in the semiconductor layer, the NWELL region including a semiconductor component;
- and
- a sacrificial NWELL region in the semiconductor layer, wherein the sacrificial NWELL region is separated from the NWELL region by a white space region in the semiconductor layer.
Dependencies are inferred from the claim text.