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US 11,901,458 B2Granted
Dielectric isolation layer between a nanowire transistor and a substrate
AssigneeIntel Corporation
InventorsBruce E. Beattie, Leonard Guler, Biswajeet Guha, Jun Sung Kang, William Hsu
Life of this patent
Estimating the term…
Abstract
Gate all around semiconductor devices, such as nanowire or nanoribbon devices, are described that include a low dielectric constant (“low-k”) material disposed between a first nanowire closest to the substrate and the substrate. This configuration enables gate control over all surfaces of the nanowires in a channel region of a semiconductor device via the high-k dielectric material, while also preventing leakage current from the first nanowire into the substrate.
Claims22
An integrated circuit device comprising:
- a nanowire over a substrate, the nanowire comprising a first semiconductor material;
- a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
- a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
- a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
- a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, and the source region and the drain region having a bottommost surface below the uppermost surface of the first dielectric layer;
- and
- first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.
4 more elements
A computing device, comprising:
- a board;
- and
- a component coupled to the board, the component including an integrated circuit structure, comprising:
- a nanowire over a substrate, the nanowire comprising a first semiconductor material;
- a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
- a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
- a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
- a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, and the source region and the drain region having a bottommost surface below the uppermost surface of the first dielectric layer;
- and
- first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.
7 more elements
An integrated circuit device comprising:
- a nanowire over a substrate, the nanowire comprising a first semiconductor material;
- a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
- a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
- a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
- a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire, wherein first portions of the source region and the drain region are in direct contact with the substrate, and the first dielectric layer is on the substrate between second portions of the source region and the drain region;
- and
- first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region.
4 more elements
An integrated circuit device comprising:
- a nanowire over a substrate, the nanowire comprising a first semiconductor material;
- a first dielectric layer between the substrate and the nanowire, the first dielectric layer comprising a first dielectric material having a first dielectric constant, and the first dielectric layer having an uppermost surface;
- a second dielectric layer completely surrounding a channel region of the nanowire, the second dielectric layer comprising a second dielectric material having a dielectric constant greater than the first dielectric constant, a portion of the second dielectric layer in contact with the first dielectric layer;
- a gate electrode completely surrounding the channel region of the nanowire and in contact with the second dielectric layer;
- a source region and a drain region comprising a second semiconductor material, the source region and the drain region on opposing sides of the nanowire;
- and
- first and second gate spacers, wherein the first gate spacer is between the second dielectric material and one of the source region or drain region, and the second gate spacer is between the second dielectric material and the other of the source region or drain region, wherein the first and second gate spacers each includes multiple portions that are discontinuous from one another.
4 more elements
Dependencies are inferred from the claim text.