FinFET devices with a backside power rail and a backside self-aligned via disposed between dielectric fins

A semiconductor structure, comprising:

• a power rail on a back side of the semiconductor structure;
• a source feature, a drain feature, a first semiconductor fin, and a gate structure on a front side of the semiconductor structure, wherein the source feature and the drain feature sandwich the first semiconductor fin, and the gate structure engages a channel region of the first semiconductor fin;
• an isolation structure disposed between the power rail and the first semiconductor fin;
• a via connecting one of the source and the drain features to the power rail;
• and
• a first dielectric fin and a second dielectric fin that are lengthwise parallel to the first semiconductor fin and sandwich the first semiconductor fin, wherein the via extends from the first dielectric fin to the second dielectric fin along a direction perpendicular to a lengthwise direction of the first semiconductor fin.

A semiconductor structure, comprising:

• a power rail on a back side of the semiconductor structure;
• a source feature, a drain feature, a first semiconductor fin, and a gate structure on a front side of the semiconductor structure, wherein the first semiconductor fin connects the source feature and the drain feature, and the gate structure engages a channel region of the first semiconductor fin;
• an isolation structure disposed between the power rail and the drain feature and between the power rail and the first semiconductor fin;
• a via disposed between the source feature and the power rail and electrically connecting the source feature to the power rail;
• and
• a dielectric barrier layer between the first semiconductor fin and the via and between the isolation structure and the via;
• and
• a first dielectric fin and a second dielectric fin that are lengthwise parallel to the first semiconductor fin and sandwich the first semiconductor fin, wherein the via extends from the first dielectric fin to the second dielectric fin along a direction perpendicular to a lengthwise direction of the first semiconductor fin.