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US 11,901,452 B2Granted
Source/drain structure having multi-facet surface
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Lien Huang, Tung Ying Lee, Winnie Chen
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Abstract
A fin-like field-effect transistor (FinFET) device is disclosed. The device includes a semiconductor substrate having a source/drain region, a plurality of isolation regions over the semiconductor substrate and a source/drain feature in the source/drain region. The source/drain feature includes a multiple plug-type portions over the substrate and each of plug-type portion is isolated each other by a respective isolation region. The source/drain feature also includes a single upper portion over the isolation regions. Here the single upper portion is merged from the multiple plug-type portions. The single upper portion has a flat top surface facing away from a top surface of the isolation region.
Claims20
A device comprising:
- a semiconductor fin structure disposed over a substrate;
- a dielectric isolation structure disposed on the substrate;
- a gate structure disposed over a first portion of the semiconductor fin structure;
- and
- a source/drain feature disposed over a second portion of the semiconductor fin structure, the source/drain feature including:
- a first lower portion and a second lower portion that are isolated from each other by the dielectric isolation structure;
- and
- a single upper portion disposed over the first and second lower portions, wherein the single upper portion is merged from the first and second lower portions, wherein the single upper portion has a top surface facing away from a top surface of the substrate, wherein the top surface of the single upper portion includes a first multi-facet surface and a flat surface interfacing with the first multi-facet surface, the first multi-facet surface being positioned at a higher level above the substrate than the flat surface and the flat surface being parallel to a top surface of the substrate, wherein the single upper portion further includes a bottom surface that opposes the flat surface of the top surface of the single upper portion, the bottom surface of the single upper portion facing the substrate and interfacing with a top surface of the dielectric isolation structure, the top surface of the dielectric isolation structure facing away from the substrate, and
- wherein the first lower portion interfaces with a first portion of the semiconductor fin structure, the first portion of the semiconductor fin structure extending to a first height above the substrate,
- wherein the dielectric isolation structure interfaces with the first portion of the semiconductor fin structure and extends to a second height over the substrate, the second height being different than the first height, and
- wherein the single upper portion and the first and second lower portions are formed of the same material, wherein the material includes a material selected from the group consisting of SiGe and SiC.
8 more elements
A device comprising:
- a first fin structure disposed over a substrate;
- a gate structure disposed over the first fin structure;
- a dielectric isolation structure disposed on the substrate;
- and
- a source/drain feature disposed over the first fin structure, the source/drain feature including:
- first and second semiconductor portions that are separated from each other by the dielectric isolation structure, wherein the first semiconductor portion physically contacts the first fin structure;
- and
- a single upper semiconductor portion disposed over the first and second semiconductor portions, wherein the single upper semiconductor portion is merged from the first and second semiconductor portions, wherein the single upper portion has a top surface facing away from a top surface of the substrate, wherein the top surface of the single upper portion includes a first multi-facet surface and a first flat surface interfacing with the first multi-facet surface, the first multi-facet surface being positioned at a higher level above the substrate than the first flat surface and the first flat surface being parallel to the top surface of the substrate, and wherein the single upper semiconductor portion and the first and second semiconductor portions are formed of the same material.
5 more elements
A device comprising:
- a fin structure disposed over a substrate;
- a gate structure disposed over the fin structure;
- an isolation structure disposed on the substrate;
- and
- a source/drain feature disposed over the fin structure, the source/drain feature including:
- first and second lower portions that are separated from each other by the isolation structure;
- a single upper semiconductor portion disposed over the first and second lower portions, wherein the single upper semiconductor portion is merged from the first and second lower portions;
- and
- a semiconductor layer disposed directly on the single upper semiconductor portion, wherein the semiconductor layer has a top surface facing away from a top surface of the substrate, wherein the top surface of the semiconductor layer includes a first multi-facet surface, wherein the semiconductor layer is formed of a different material than the single upper semiconductor portion.
6 more elements
Dependencies are inferred from the claim text.