High voltage isolation devices for semiconductor devices

A semiconductor device, comprising:

• an active area having a column of bit line contacts;
• a first gate over the active area, the first gate including a straight portion and a plurality of protruded segments connected to the straight portion, each protruded segment extending past an edge of the active area and located between two neighboring bit line contacts;
• a plurality of active channels connected to the active area, each active channel aligned with a corresponding bit line contact;
• and
• a second gate over the plurality of active channels, the second gate extending in a direction parallel to the column of bit line contacts.

A semiconductor device, comprising:

• a first active area having a column of first bit line contacts;
• a plurality of first active channels connected to the first active region, each first active channel aligned with a corresponding first bit line contact;
• a second active area having a column of second bit line contacts;
• and
• a plurality of second active channels connected to the second active area, each second active channel aligned with a corresponding second bit line contact,
• wherein:
• the plurality of first active channels extend toward the second active area;
• the plurality of second active channels extend toward the first active area;
• and
• the plurality of first active channels and the plurality of second active channels form a plurality of interdigitated active channels such that individual first active channels alternate with individual second active channels.