US 11,901,446 B2Granted

SiC MOSFET with transverse P+ region

AssigneeUnity Power Technology Limited

InventorKuk Fong Yip

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Abstract

A silicon carbide MOSFET device that includes a silicon carbide substrate of a first dopant type; a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate; a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer; a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer; a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer; and a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate. The first silicon carbide layer has lower doping than the silicon carbide substrate and defines a drift region. The third silicon carbide layer has higher doping than the first silicon carbide layer. The third silicon carbide layer includes a plurality of third portions that run substantially along a first direction. The second silicon carbide layer includes a plurality of second portions that run substantially along the first direction. The fourth silicon carbide layer includes a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction. The first and second directions each is parallel to the silicon carbide substrate. The transversely arranged P+ regions to N+ regions in some embodiments allow adequate P+ area to achieve good body diode performance and protection to the gate oxide, but without consuming significant area of the MOSFET cell.

Claims20

Dependent claims

A silicon carbide MOSFET device, comprising:

a) a silicon carbide substrate of a first dopant type;
b) a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate, the first silicon carbide layer having lower doping than the silicon carbide substrate and defining a drift region;
c) a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer;
the second silicon carbide layer comprising a plurality of second portions that run substantially along a first direction;
d) a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer;
the third silicon carbide layer having higher doping than the first silicon carbide layer;
the third silicon carbide layer comprising a plurality of third portions that run substantially along the first direction;
and
e) a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer;
and in touch with a polysilicon layer;
wherein, the device further comprises a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate;
the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprising a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction;
the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P:
the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction;
the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction;
and
wherein the second silicon carbide layer comprises a plurality of P-well regions separated from each other along the second direction.

15 more elements

A silicon carbide MOSFET device, comprising:

a) a silicon carbide substrate of a first dopant type;
b) a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate, the first silicon carbide layer having lower doping than the silicon carbide substrate and defining a drift region;
c) a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer;
the second silicon carbide layer comprising a plurality of second portions that run substantially along a first direction;
d) a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer;
the third silicon carbide layer having higher doping than the first silicon carbide layer;
the third silicon carbide layer comprising a plurality of third portions that run substantially along the first direction;
and
e) a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer;
and in touch with a polysilicon layer;
wherein, the device further comprises a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate;
the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprising a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction;
the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P:
the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction;
the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction;
and
wherein the third silicon carbide layer comprises two N+ regions as the third portions which are disposed respectively on two opposite sides of the gate oxide layer.

15 more elements

A silicon carbide MOSFET device, comprising:

a) a silicon carbide substrate of a first dopant type;
b) a first silicon carbide layer of the first dopant type on top of the silicon carbide substrate, the first silicon carbide layer having lower doping than the silicon carbide substrate and defining a drift region;
c) a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer;
the second silicon carbide layer comprising a plurality of second portions that run substantially along a first direction;
d) a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer;
the third silicon carbide layer having higher doping than the first silicon carbide layer;
the third silicon carbide layer comprising a plurality of third portions that run substantially along the first direction;
and
e) a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer;
and in touch with a polysilicon layer;
wherein, the device further comprises a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate;
the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprising a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction;
the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P:
the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction;
the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction;
and
wherein the P+ portions are doped using multiple consecutive ion implantations with a double-peak profile.

15 more elements

A method of producing a silicon carbide MOSFET device, comprising the steps of:

a) providing a first silicon carbide layer of a first dopant type on top of a silicon carbide substrate;
the first silicon carbide layer comprises first epitaxy layer and second epitaxy layer, which have same or different doping but both have lower doping than the silicon carbide substrate;
b) providing a second silicon carbide layer of a second dopant type embedded in a top portion of the first silicon carbide layer;
c) providing a third silicon carbide layer of the first dopant type embedded in a top portion of the second silicon carbide layer;
the third silicon carbide layer having higher doping than the first silicon carbide layer;
the third silicon carbide layer comprising a plurality of third portions that run substantially along a first direction;
d) providing a gate oxide layer overlapped to the first silicon carbide layer, the second silicon carbide layer and the third silicon carbide layer;
and in touch with a polysilicon layer;
and
e) providing a fourth silicon carbide layer at least partially overlapping with the second silicon carbide layer along a direction normal to the silicon carbide substrate;
the fourth silicon carbide layer, which has higher doping than the second silicon carbide layer, comprises a plurality of fourth portions that run substantially along a second direction perpendicular to the first direction;
the first and second directions each being parallel to the silicon carbide substrate;
wherein the first dopant type is N and the second dopant type is P:
the third silicon carbide layer being a N+ layer, and the third portions of the third silicon carbide layer being separated from each other along the second direction;
the fourth silicon carbide layer being a P+ layer, and the fourth portions are P+ portions which are separated from each other along the first direction;
and
wherein the second silicon carbide layer comprises a plurality of P-well regions separated from each other along the second direction.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/405,114Filed 18 Aug 2021
Published: US 2023/0053874 A123 Feb 2023
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10D 84/144
The built-in components being PN junction diodes: in antiparallel diode configurations
H10D 12/031
Manufacture or treatment: of igbts
H10D 30/0291
Of double-diffused metal oxide semiconductor [DMOS] FETs: of vertical dmos [vdmos] fets
H10D 30/0297
Of vertical dmos [vdmos] fets: using recessing of the gate electrodes, e.g. to form trench gate electrodes