Semiconductor device and method

A semiconductor device comprising:

• a semiconductor substrate;
• a channel region on the semiconductor substrate;
• a gate structure on the channel region;
• a source/drain region adjacent the gate structure;
• and
• an inner spacer adjacent the channel region, wherein the inner spacer is between the source/drain region and the gate structure, wherein the inner spacer comprises:
• a first inner spacer layer contacting the gate structure and the source/drain region;
• a second inner spacer layer contacting the first inner spacer layer and the source/drain region;
• and
• a third inner spacer layer contacting the second inner spacer layer and the source/drain region, wherein a first sidewall of the inner spacer adjacent the source/drain region is W-shaped in a cross-sectional view, wherein a second sidewall of the inner spacer adjacent the gate structure is U-shaped in the cross-sectional view, wherein the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer comprise carbon, and wherein a first atomic percentage of carbon in the first inner spacer layer is greater than a second atomic percentage of carbon in the second inner spacer layer and a third atomic percentage of carbon in the third inner spacer layer.

A method comprising:

• forming a first semiconductor layer on a semiconductor substrate, the first semiconductor layer comprising a first semiconductor material;
• etching sidewalls of the first semiconductor layer to form a sidewall recess;
• depositing a first inner spacer layer in the sidewall recess;
• depositing a second inner spacer layer on the first inner spacer layer;
• depositing a third inner spacer layer filling the sidewall recess;
• etching the first inner spacer layer, the second inner spacer layer, and the third inner spacer layer to form an inner spacer in the sidewall recess, wherein the second inner spacer layer is etched at a rate greater than the third inner spacer layer;
• etching the first semiconductor layer and the first inner spacer layer to form a first recess adjacent the inner spacer, wherein the first inner spacer layer is etched at a rate less than the first semiconductor layer;
• and
• forming a gate structure in the first recess.