RF switch device with a sidewall spacer having a low dielectric constant
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorCheng-Ta Wu
Life of this patent
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Abstract
Various embodiments of the present disclosure are directed towards a method for forming an integrated circuit (IC). The method includes forming a gate electrode and a gate dielectric stacked over a substrate. A sidewall liner is formed along sidewalls of the gate electrode and along an upper surface of the substrate. A sidewall spacer is formed on sidewalls and an upper surface of the sidewall liner. The sidewall spacer consists essentially of silicon oxycarbonitride and has a dielectric constant great than that of the sidewall liner and less than that of the gate dielectric. A pair of source/drain regions is formed respectively on opposite sides of the gate electrode.
Claims20
A method for forming an integrated circuit (IC), the method comprising:
- forming a gate electrode and a gate dielectric stacked over a substrate;
- forming a sidewall liner along sidewalls of the gate electrode and along an upper surface of the substrate;
- forming a sidewall spacer on sidewalls and an upper surface of the sidewall liner, wherein the sidewall spacer consists essentially of silicon oxycarbonitride and has a dielectric constant greater than that of the sidewall liner and less than that of the gate dielectric;
- and
- forming a pair of source/drain regions respectively on opposite sides of the gate electrode.
A method for forming a semiconductor structure, the method comprising:
- forming a gate structure over a substrate;
- depositing a sidewall spacer layer covering the substrate and lining sidewalls of the gate structure;
- performing an etching process on the sidewall spacer layer to form a sidewall spacer on the sidewalls of the gate structure, wherein an etch rate of the sidewall spacer layer during the etching process is greater than 1 angstroms/minute and less than about 8 angstroms/minute and is performed at a temperature within a range of about 600 to 650 degrees Celsius;
- and
- forming a pair of source/drain regions within the substrate on opposing sides of the gate structure.
A method for forming a semiconductor structure, the method comprising:
- forming an isolation structure in a substrate, wherein the substrate comprises a device layer, a high resistivity layer under the device layer, and an insulator layer between the device layer and the high resistivity layer;
- forming a gate dielectric layer on the device layer;
- forming a gate electrode on the gate dielectric layer;
- depositing a sidewall spacer layer on the device layer and along sidewalls of the gate electrode, wherein the sidewall spacer layer has a dielectric constant greater than that of the insulator layer and less than that of the gate dielectric layer, wherein the sidewall spacer layer is deposited at a first ambient temperature within a first temperature range;
- and
- etching the sidewall spacer layer to define a sidewall spacer on the sidewalls of the gate electrode, wherein the sidewall spacer layer is etched at a second ambient temperature within a second temperature range, wherein the first temperature range includes the second temperature range.
Dependencies are inferred from the claim text.