Semiconductor device

A device, comprising:

• a first III-V compound layer;
• a second III-V compound layer over the first III-V compound layer;
• a source/drain contact over the second III-V compound layer, wherein a bottom portion of the source/drain contact is embedded in the second III-V compound layer, and an ohmic connection is formed between the source/drain contact and the second III-V compound layer;
• a dielectric layer over the second III-V compound layer and laterally surrounding the source/drain contact;
• a metal contact over the source/drain contact;
• and
• an etch stop layer over the source/drain contact and laterally surrounding the metal contact.

A device, comprising:

• a first III-V compound layer;
• a second III-V compound layer over the first III-V compound layer;
• a source contact and a drain contact over the second III-V compound layer, wherein an ohmic connection is formed between the source contact and the second III-V compound layer;
• a first metal-containing layer and a second metal-containing layer respectively over the source contact and the drain contact;
• a gate field plate over the second III-V compound layer and between the source contact and the drain contact, wherein the gate field plate is made of a material a same as a material of the first metal-containing layer;
• and a first oxide layer and a second oxide layer respectively over the first metal-containing layer and the second metal-containing layer, wherein a sidewall of the first oxide layer is substantially aligned with a sidewall of the first metal-containing layer.