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US 11,901,432 B2Granted
And manufacture of self-aligned power devices
AssigneeGeneSiC Semiconductor Inc.
InventorsSiddarth Sundaresan, Ranbir Singh, Jaehoon Park
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Abstract
An embodiment relates to a method comprising obtaining a SiC substrate comprising a N+ substrate and a N− drift layer; depositing a first hard mask layer on the SiC substrate and patterning the first hard mask layer; performing a p-type implant to form a p-well region; depositing a second hard mask layer on top of the first hard mask layer; performing an etch back of at least the second hard mask layer to form a sidewall spacer; implanting N type ions to form a N+ source region that is self-aligned; and forming a MOSFET.
Claims18
A method comprising:
- obtaining a Silicon Carbide (SiC) wafer comprising a first conductivity type drift layer on a first conductivity type substrate;
- forming a first mask layer and patterning the first mask layer on the SiC wafer;
- implanting ions of a second conductivity type to form a first well region;
- depositing a second mask layer over the first mask layer;
- etching the second mask layer to form a sidewall spacer over the first mask layer;
- subsequently implanting ions of a first conductivity type to form a source region;
- and
- subsequently removing the first mask layer and the second mask layer;
- and
- wherein the method further comprises:
- patterning a gate metal layer in a peripheral region to result in a segmented pattern and disjointed gate fingers, wherein the disjointed gate fingers comprise an electrical connection at selected locations.
8 more elements
Dependencies are inferred from the claim text.