Semiconductor device with backside gate isolation structure and method for forming the same

A method, comprising:

• receiving a workpiece having a frontside and a backside, the workpiece including:
• a first plurality of semiconductor layers over a first base portion on a frontside surface of a substrate and a second plurality of semiconductor layers over a second base portion on the frontside surface of the substrate;
• a first dielectric feature on a first side of the first plurality of the semiconductor layers and between the first plurality of the semiconductor layers and the second plurality of the semiconductor layers;
• and
• a second dielectric feature on a second side of the first plurality of the semiconductor layers, the second side being opposite to the first side, and the second dielectric feature having a feature surface facing the frontside;
• forming a gate structure engaging the first plurality of semiconductor layers and the second plurality of semiconductor layers and interfacing with the first dielectric feature on the feature surface;
• replacing the first base portion and the second base portion to form a first backside dielectric and a second backside dielectric, respectively;
• removing the first dielectric feature but not the second dielectric feature, thereby forming an opening between the first plurality of semiconductor layers and the second plurality of semiconductor layers;
• recessing the gate structure from the opening to form a gate cut opening, the gate cut opening extending from a front surface of the gate structure to a back surface of the gate structure;
• forming a third dielectric feature in the gate cut opening.

A method, comprising:

• receiving a workpiece having a frontside and a backside facing away from each other along a vertical direction, the workpiece including a first stack of semiconductor layers over a first base portion on a frontside surface of a substrate and a second stack of semiconductor layers over a second base portion on the frontside surface of the substrate, wherein the first stack and the second stack each include first semiconductor layers and second semiconductor layers vertically arranged interleavingly, wherein the first stack and the second stack each extend lengthwise along a first direction, and wherein an isolation feature interposes between the first base portion and the second base portion;
• forming a hybrid structure between sidewall surfaces of the first stack and the second stack and on a first surface of the isolation feature, wherein the hybrid structure includes a first low-k dielectric layer wrapped by a first high-k dielectric layer, and a second high-k dielectric layer on the first low-k dielectric layer and on the first high-k dielectric layer;
• forming a first gate stack on the first stack and the second stack along a second direction perpendicular to the first direction, the first gate stack covering a portion of the second high-k dielectric layer;
• forming source/drain features on both sides of the first gate stack;
• recessing a portion of the second high-k dielectric layer not covered by the first gate stack;
• selectively removing the second semiconductor layers;
• recessing the first high-k dielectric layer on sidewall surfaces of the first low-k dielectric layer;
• forming a gate dielectric layer surrounding the first semiconductor layers and surrounding the first low-k dielectric layer, a gate electrode layer surrounding the gate dielectric layer, and a gate cap covering the gate electrode layer;
• replacing the first base portion and the second base portion from the backside to form a backside dielectric layer;
• and
• forming a gate cut feature extending vertically through the backside dielectric layer, through the gate electrode layer, and through the gate cap.