US 11,901,416 B2Granted

Semiconductor device

AssigneeMitsubishi Electric Corporation

InventorTetsujiro Tsunoda

Life of this patent

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Abstract

An object is to provide a technique capable of suppressing the rise in the sense voltage during the Miller plateau. A semiconductor device includes a semiconductor substrate of first conductivity type, a first IGBT portion and a second IGBT portion selectively disposed on a first main surface of the semiconductor substrate, and an impurity region of second conductivity type selectively disposed on a second main surface of the semiconductor substrate. The second IGBT portion is used to detect the current passing through the first IGBT portion. An area ratio of the impurity region within a second range to an area of the second range is lower than an area ratio of the impurity region within a first range to an area of the first range, the second range corresponding to the second IGBT portion, the first range corresponding to the first IGBT portion.

Claims5

Dependent claims

A semiconductor device, comprising:

a semiconductor substrate of first conductivity type;
a first IGBT portion selectively disposed on a first main surface of the semiconductor substrate;
a second IGBT portion disposed on the first main surface of the semiconductor substrate, spaced from the first IGBT portion, and used for detection of a current passing through the first IGBT portion;
and
an impurity region of second conductivity type selectively disposed on a second main surface opposite to the first main surface of the semiconductor substrate, wherein
an area ratio of the impurity region within a second range to an area of the second range is lower than an area ratio of the impurity region within a first range to an area of the first range, the second range corresponding to the second IGBT portion on the second main surface, the first range corresponding to the first IGBT portion on the second main surface.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/418,511Filed 10 Apr 2019
Published: US 2022/0069086 A13 Mar 2022
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10D 62/127
Top-view geometrical layouts of the regions or the junctions: of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
H10D 62/393
Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions: body regions of…
H10D 12/481
Having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions: having gate…
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]