Diffusion barrier layer for source and drain structures to increase transistor performance
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsKuei-Ming Chen, Chi-Ming Chen, Chung-Yi Yu
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Abstract
Various embodiments of the present disclosure are directed towards a semiconductor device including a gate electrode over a semiconductor substrate. An epitaxial source/drain layer is disposed on the semiconductor substrate and is laterally adjacent to the gate electrode. The epitaxial source/drain layer comprises a first dopant. A diffusion barrier layer is between the epitaxial source/drain layer and the semiconductor substrate. The diffusion barrier layer comprises a barrier dopant that is different from the first dopant.
Claims20
A semiconductor device, comprising:
- a gate electrode overlying a semiconductor substrate;
- an epitaxial source/drain layer disposed on the semiconductor substrate and laterally adjacent to the gate electrode, wherein the epitaxial source/drain layer comprises a first dopant;
- and
- a diffusion barrier layer between the epitaxial source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer is co-doped with the first dopant and a barrier dopant that is different from the first dopant, wherein a doping concentration of the barrier dopant within the diffusion barrier layer is less than a doping concentration of the first dopant within the diffusion barrier layer, wherein a doping profile of the barrier dopant in the diffusion barrier layer comprises a gaussian distribution.
An integrated chip, comprising:
- a semiconductor-on-insulator (SOI) substrate comprising a first semiconductor layer, a second semiconductor layer, and an insulating layer disposed between the first and second semiconductor layers;
- an N-type metal oxide semiconductor (NMOS) transistor disposed over the first semiconductor layer, wherein the NMOS transistor comprises a gate electrode, a gate dielectric layer disposed between the gate electrode and the first semiconductor layer, and a pair of source/drain structures disposed on opposing sides of the gate electrode, wherein the pair of source/drain structures comprise:
- a first pair of epitaxial source/drain layers over the first semiconductor layer, wherein the first pair of source/drain epitaxial layers comprise a first N-type dopant;
- and
- diffusion barrier layers disposed between the first semiconductor layer and the first pair of source/drain epitaxial layers, wherein the diffusion barrier layers comprise a barrier dopant that is different from the first N-type dopant, wherein the diffusion barrier layers extend continuously from a top surface of the first semiconductor layer to a top surface of the insulating layer.
An integrated chip, comprising:
- a gate structure overlying a semiconductor substrate;
- a source/drain layer disposed on the semiconductor substrate and adjacent a side of the gate structure, wherein the source/drain layer comprises a first dopant;
- and
- a diffusion barrier layer between the source/drain layer and the semiconductor substrate, wherein the diffusion barrier layer comprises a second dopant different from the first dopant, wherein a doping concentration of the second dopant within the diffusion barrier layer is less than a doping concentration of the first dopant within the source/drain layer, and wherein a thickness of the diffusion barrier layer is less than a thickness of the source/drain layer, wherein a region of the semiconductor substrate directly contacting a bottom surface of the diffusion barrier layer has a doping type opposite the first dopant.
Dependencies are inferred from the claim text.