US 11,901,364 B2Granted

Semiconductor device structure and methods of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsJung-Hung Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang

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Abstract

A semiconductor device structure, along with methods of forming such, are described. The structure includes a plurality of semiconductor layers having a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers. The structure further includes a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers and a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers. The first number of semiconductor layers of the first group of semiconductor layers is different from the second number of semiconductor layers of the third group of semiconductor layers.

Claims20

Dependent claims

A semiconductor device structure, comprising:

a first plurality of semiconductor layers disposed at a first location of the semiconductor device structure, wherein the first plurality of semiconductor layers comprises a first group of semiconductor layers, a second group of semiconductor layers disposed over and aligned with the first group of semiconductor layers, and a third group of semiconductor layers disposed over and aligned with the second group of semiconductor layers;
a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first group of semiconductor layers, wherein the first source/drain epitaxial feature has a first height;
a first dielectric material disposed over the first source/drain epitaxial feature;
a second source/drain epitaxial feature in contact with a second number of semiconductor layers of the third group of semiconductor layers, wherein the second source/drain epitaxial feature is disposed over the first dielectric material;
a second plurality of semiconductor layers disposed at a second location of the semiconductor device structure, wherein the second plurality of semiconductor layers comprises a fourth group of semiconductor layers, a fifth group of semiconductor layers disposed over and aligned with the fourth group of semiconductor layers, and a sixth group of semiconductor layers disposed over and aligned with the fifth group of semiconductor layers;
a third source/drain epitaxial feature in contact with a third number of semiconductor layers of the fourth group of semiconductor layers, wherein the third source/drain epitaxial feature has a second height different from the first height;
a second dielectric material disposed over the third source/drain epitaxial feature;
and
a fourth source/drain epitaxial feature in contact with a fourth number of semiconductor layers of the sixth group of semiconductor layers, wherein the fourth source/drain epitaxial feature is disposed over the second dielectric material.

6 more elements

A semiconductor device structure, comprising:

a first plurality of semiconductor layers disposed at a first location of the semiconductor device structure;
a second plurality of semiconductor layers disposed at a second location of the semiconductor device structure, wherein the semiconductor layers of the second plurality of semiconductor layers are disposed at same levels as corresponding semiconductor layers of the first plurality of semiconductor layers;
a third plurality of semiconductor layers disposed at a third location of the semiconductor device structure, wherein the semiconductor layers of the third plurality of semiconductor layers are disposed at same levels as corresponding semiconductor layers of the second plurality of semiconductor layers;
a first source/drain epitaxial feature in contact with a first number of semiconductor layers of the first plurality of semiconductor layers, wherein the first source/drain epitaxial feature has a first height;
a first dielectric material disposed over the first source/drain epitaxial feature, wherein the first dielectric material is disposed adjacent a second number of semiconductor layers of the first plurality of semiconductor layers;
a second source/drain epitaxial feature disposed over the first dielectric material, wherein the second source/drain epitaxial feature is in contact with a third number of semiconductor layers of the first plurality of semiconductor layers;
a third source/drain epitaxial feature in contact with a fourth number of semiconductor layers of the second plurality of semiconductor layers, wherein the third source/drain epitaxial feature has a second height different from the first height;
a second dielectric material disposed over the third source/drain epitaxial feature, wherein the second dielectric material is disposed adjacent a fifth number of semiconductor layers of the second plurality of semiconductor layers;
and
a fourth source/drain epitaxial feature disposed over the second dielectric material, wherein the fourth source/drain epitaxial feature is in contact with a sixth number of semiconductor layers of the second plurality of semiconductor layers.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/459,101Filed 27 Aug 2021
Published: US 2023/0064705 A12 Mar 2023
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification24 codes

H10D 87/00
Integrated devices comprising both bulk components and either soi or sos components
H10D 30/019
Manufacture or treatment: of FETs having stacked nanowire, nanosheet or nanoribbon channels
H10D 30/0198
Of FETs having stacked nanowire, nanosheet or nanoribbon channels: forming source or drain electrodes wherein semiconductor bodies are replaced by…
H10D 30/501
Field-effect transistors [FET]: fETs having stacked nanowire, nanosheet or nanoribbon channels