Semiconductor device and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsin-Yi Lee, Weng Chang, Chi On Chui
Life of this patent
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Abstract
In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a n-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a p-type work function metal, the p-type work function metal different from the n-type work function metal; and a fill layer on the second work function tuning layer.
Claims20
A device comprising:
- first nanostructures;
- a gate dielectric on the first nanostructures;
- and
- a first gate electrode comprising:
- a first layer on the gate dielectric, the first layer comprising an n-type work function metal, the first layer being disposed in an area between the first nanostructures;
- a second layer on the first layer, the second layer comprising a barrier material, the barrier material being different from the n-type work function metal, the area between the first nanostructures being free of the second layer;
- and
- a third layer on the second layer, the third layer comprising a p-type work function metal, the p-type work function metal being different from the n-type work function metal, the p-type work function metal being different from the barrier material.
A method comprising:
- forming a first set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region;
- forming first source/drain regions adjacent the first channel region of the first set of nanostructures;
- forming a first gate dielectric on the first channel region;
- forming a first work function tuning layer on the first gate dielectric;
- forming a barrier layer on the first work function tuning layer;
- forming a second work function tuning layer on the barrier layer;
- performing a treatment process on the second work function tuning layer to modify a second work function of the second work function tuning layer;
- and
- depositing a fill layer on the treated second work function tuning layer.
A method comprising:
- forming a first set of nanostructures and a second set of nanostructures on a substrate, the first set of nanostructures comprising a first channel region and the second set of nanostructures comprising a second channel region;
- forming a gate dielectric layer having a first portion and a second portion, the first portion deposited on the first channel region, the second portion deposited on the second channel region;
- forming a n-type work function tuning layer on the first portion of the gate dielectric layer and the second portion of the gate dielectric layer, the n-type work function tuning layer wrapping around each of the first set of nanostructures;
- forming a first barrier layer on the n-type work function tuning layer;
- removing the first barrier layer and the n-type work function tuning layer from the second portion of the gate dielectric layer;
- forming a p-type work function tuning layer on the first barrier layer on the first set of nanostructures and the second portion of the gate dielectric layer;
- performing a treatment process on the p-type work function tuning layer to modify a work function of the p-type work function tuning layer;
- and
- forming a fill layer on the p-type work function tuning layer.
Dependencies are inferred from the claim text.