Semiconductor device with gate electrode with flat upper surface and no protruding portion and methods of manufacturing the same

A semiconductor device, comprising:

• first and second active patterns disposed on first and second regions of a substrate, respectively, wherein each of the first and second active patterns protrudes from the substrate and extends in a first direction substantially parallel to an upper surface of the substrate;
• an isolation pattern disposed on the substrate and that covers lower sidewalls of the first and second active patterns;
• a first gate structure that extends in a sedond direction on the first active patterns and the isolation pattern, wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction;
• a second gate structure that extends in the second direction on the second drive patterns and the isolation pattern;
• a first division pattern structure disposed on the first region of the substrate, wherein the first division pattern structure contacts a sidewall of an end portion in the second direction of the first gate structure;
• and
• a second division pattern disposed on the second region of the substrate, wherein the second division pattern contacts a sidewall of an end portion in the second direction of the second gate structure,
• wherein an uppermost surface of the first gate structure is higher than an uppermost surface of the second gate structure, and
• wherein the upper surface of the portion of the first gate structure on the sidewall of the first division pattern structure is lower than an upper surface of the first division pattern structure.

A semiconductor device, comprising:

• first and second active patterns disposed on first and second regions of a substrate, respectively, wherein each of the first and second active patterns protrudes from the substrate and extends in a first direction substantially parallel to an upper surface of the substrate;
• an isolation pattern disposed on the substrate and that covers lower sidewalls of the first and second active patterns;
• a first gate structure that extends in a second direction on the first active patterns and the isolation pattern, wherein the second direction is substantially parallel to the upper surface of the substrate and crosses the first direction;
• a second gate structure that extends in the second direction on the second active patterns and the isolation pattern;
• a first division pattern structure disposed on the first region of the substrate, wherein the first division pattern structure contacts a sidewall of an end portion in the second direction of the first gate structure, wherein the first division pattern structure includes a first insulation pattern, a second insulation pattern and a third insulation pattern that are sequentially stacked;
• and
• a second division pattern disposed on the second region of the substrate, wherein the second division pattern contacts a sidewall of an end portion in the second direction of the second gate structure,
• wherein an uppermost surface of the first gate structure is higher than an uppermost surface of the second gate structure,
• the first gate structure is one of a plurality of first gate structures that are spaced apart from each other in the first direction,
• each of the first and second insulation patterns contacts a sidewall of a corresponding first gate structure of the plurality of first gate structures, and
• the third insulation pattern includes:
• vertical extension portions that contact the sidewalls of the first gate structures, and a horizontal extension portion that commonly contacts upper surfaces of the vertical extension portions.