Semiconductor device

A semiconductor device, comprising:

• a substrate that includes a first region and a second region;
• a first active pattern on the first region, the first active pattern including a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns;
• a second active pattern on the second region, the second active pattern including a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns;
• and
• a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern,
• wherein:
• a length of the first channel pattern is greater than a length of the second channel pattern,
• the first channel pattern includes a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked on the substrate,
• the first gate electrode includes:
• a first part between the substrate and the first semiconductor pattern;
• a second part between the first semiconductor pattern and the second semiconductor pattern;
• and
• a third part between the second semiconductor pattern and the third semiconductor pattern,
• a thickness of one of the second part and the third part decreases from a center point thereof to an edge point thereof, and
• a thickness of another of the second part and the third part increases from a center point thereof to an edge point thereof.

A semiconductor device, comprising:

• a substrate that includes a peripheral region and a logic cell region;
• a device isolation layer that defines a first active pattern on the peripheral region and a second active pattern on the logic cell region;
• a pair of first source/drain patterns on the first active pattern and a pair of second source/drain patterns on the second active pattern;
• a first channel pattern between the pair of first source/drain patterns and a second channel pattern between the pair of second source/drain patterns, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked on the substrate;
• a first gate electrode on the first channel pattern and a second gate electrode on the second channel pattern;
• a first gate dielectric layer between the first channel pattern and the first gate electrode and a second gate dielectric layer between the second channel pattern and the second gate electrode;
• a pair of gate spacers on opposite sides of each of the first gate electrode and the second gate electrode;
• a gate capping pattern on a top surface of each of the first gate electrode and the second gate electrode;
• a plurality of active contacts electrically connected to the first source/drain pattern and the second source/drain pattern;
• a plurality of gate contacts electrically connected to the first gate electrode and the second gate electrode;
• a first metal layer on the active contacts and the gate contacts, the first metal layer including a plurality of first lines electrically connected to the active contacts and the gate contacts;
• and
• a second metal layer on the first metal layer,
• wherein:
• a length of the first channel pattern is greater than a length of the second channel pattern,
• at least two of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern of the first channel pattern are bent in a first vertical direction away from a bottom surface of the substrate or bent in a second vertical direction toward the bottom surface of the substrate, and
• a remaining one of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern of the first channel pattern is flat.