Three-dimensional semiconductor devices

A three-dimensional semiconductor device, comprising:

• a lower substrate;
• a plurality of lower transistors disposed on the lower substrate;
• an upper substrate disposed on the lower transistors;
• a lower interlayer insulating layer disposed between the lower transistors and the upper substrate;
• an upper interlayer insulating layer disposed on the upper substrate;
• a plurality of lower conductive lines disposed within the lower interlayer insulating layer between the lower transistors and the upper substrate;
• a plurality of upper transistors disposed within the upper interlayer insulating layer on the upper substrate;
• a plurality of upper conductive lines disposed on the upper transistors;
• an upper penetration via penetrating the upper interlayer insulating layer, the upper substrate, and a portion of the lower interlayer insulating layer,
• wherein a first location where an inner side of the upper penetration via and the upper interlayer insulating layer contact each other, a second location where the inner side of the upper penetration via and the upper substrate contact each other, and a third location where the inner side of the upper penetration via and the lower interlayer insulating layer contact each other are vertically aligned;
• and
• a plurality of intermediate transistors disposed within the lower interlayer insulating layer below the upper substrate,
• wherein each of the upper transistors comprises:
• an upper gate electrode disposed on the upper substrate;
• a first upper source/drain pattern disposed in the upper substrate at a first side of the upper gate electrode;
• and
• a second upper source/drain pattern disposed in the upper substrate at a second, opposing side of the upper gate electrode,
• wherein each of the lower transistors comprises:
• a lower gate electrode disposed on the lower substrate;
• a first lower source/drain pattern disposed in the lower substrate at a first side of the lower gate electrode;
• and
• a second lower source/drain pattern disposed in the lower substrate at a second, opposing side of the lower gate electrode,
• wherein the upper gate electrode comprises a polycrystalline silicon germanium (SiGe) layer that is doped with a dopant, and a concentration of the dopant in the upper gate electrode is smaller than a concentration of germanium (Ge) in the upper gate electrode,
• wherein the lower gate electrode comprises polycrystalline silicon or polycrystalline germanium,
• wherein one terminal of at least one of the lower transistors is directly connected to a corresponding one of the lower conductive lines by a lower conductive contact, and one terminal of at least one of the upper transistors is directly connected to a corresponding one of the upper conductive lines by an upper conductive contact,
• wherein the one terminal of the at least one of the lower transistors is electrically connected to the one terminal of the at least one of the upper transistors through corresponding ones of the lower conductive lines, the upper and lower conductive contacts, and corresponding ones of the upper conductive lines,
• wherein the upper penetration via extends above the upper substrate and is disposed adjacent to the upper gate electrode of at least one of the upper transistors above the upper substrate,
• wherein each of the plurality of intermediate transistors comprises:
• a back-gate electrode disposed on a bottom surface of the upper substrate;
• and
• a back-gate insulating layer interposed between the upper substrate and the back-gate electrode.