Three dimensional integrated circuit with lateral connection layer
AssigneeSilicon Genesis Corporation
InventorsMichael I. Current, Theodore E. Fong
Life of this patent
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AssigneeSilicon Genesis Corporation
InventorsMichael I. Current, Theodore E. Fong
Estimating the term…
Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.
A method for forming a three-dimensional integrated circuit (3DIC), the method comprising:
A method of forming a three-dimensional integrated circuit (3DIC), the method comprising:
Dependencies are inferred from the claim text.