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US 11,901,348 B2Granted
Semiconductor package and method of manufacturing the semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorsTae-Ho Kang, Bo-Seong Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a mold substrate, at least one first semiconductor chip in the mold substrate and including chip pads, wiring bonding pads formed at a first surface of the mold substrate and connected to the chip pads by bonding wires, and a redistribution wiring layer covering the first surface of the mold substrate and including redistribution wirings connected to the wiring bonding wirings.
Claims20
A method of manufacturing a semiconductor package, comprising:
- forming first and second wiring bonding pads on a dummy substrate;
- stacking a first semiconductor chip on the dummy substrate;
- stacking a support member on the dummy substrate such that the support member is arranged to be spaced apart from the first semiconductor chip;
- forming first bonding wires to connect first chip pads of the first semiconductor chip with the first wiring bonding pads;
- stacking a plurality of second semiconductor chips on the first semiconductor chip and the support member;
- forming second bonding wires to connect second chip pads of the second semiconductor chips with the second wiring bonding pads;
- covering the first semiconductor chip, the support member and the second semiconductor chips on the dummy substrate with a molding member to form a mold substrate;
- removing the dummy substrate from the mold substrate such that the first and second wiring bonding pads are exposed from a first surface of the mold substrate;
- and
- forming a redistribution wiring layer on the first surface of the mold substrate, the redistribution wiring layer including redistribution wirings electrically connected to the first and second wiring bonding pads.
7 more elements
A method of manufacturing a semiconductor package, comprising:
- forming first and second relay bonding pads on a dummy substrate;
- stacking a first semiconductor chip on the dummy substrate such that first chip pads are on a first surface of the first semiconductor chip, and a second surface of the first semiconductor chip that is opposite to the first surface of the first semiconductor chip faces the dummy substrate;
- forming first bonding wires to connect the first chip pads of the first semiconductor chip with the first relay bonding pads;
- stacking a plurality of second semiconductor chips on the first semiconductor chip;
- forming second bonding wires to connect second chip pads of the second semiconductor chips with the second relay bonding pads;
- covering the first semiconductor chip and the second semiconductor chips on the dummy substrate with a molding member to form a mold substrate;
- removing the dummy substrate from the mold substrate such that the first and second relay bonding pads are exposed from a first surface of the mold substrate;
- and
- forming a redistribution wiring layer on the first surface of the mold substrate, the redistribution wiring layer including redistribution wirings electrically connected to the first and second relay bonding pads.
6 more elements
Dependencies are inferred from the claim text.