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US 11,901,347 B2Granted
Microelectronic package with three-dimensional (3D) monolithic memory die
AssigneeIntel Corporation
InventorsWilfred Gomes, Mauro J. Kobrinsky, Doug B. Ingerly, Tahir Ghani
Life of this patent
Estimating the term…
Abstract
Embodiments may relate to a microelectronic package. The microelectronic package may include a memory die with: a first memory cell at a first layer of the memory die; a second memory cell at a second layer of the memory die; and a via in the memory die that communicatively couples an active die with a package substrate of the microelectronic package. Other embodiments may be described or claimed.
Claims19
A microelectronic package comprising:
- a package substrate;
- an active die;
- and
- a memory die communicatively coupled with the package substrate and the active die, wherein the memory die includes:
- a first memory cell at a first n-type metal-oxide-semiconductor (NMOS) layer of the memory die;
- a second memory cell at a second NMOS layer of the memory die;
- a complimentary metal-oxide semiconductor (CMOS) layer comprising control logic for the memory die;
- and
- a via in the memory die that communicatively couples the active die with the package substrate.
6 more elements
An electronic device comprising:
- an antenna to facilitate wireless communication between the electronic device and another electronic device;
- and
- a microelectronic package communicatively coupled with the antenna, wherein the microelectronic package includes:
- a memory die communicatively coupled with a package substrate of the electronic device, wherein the memory die comprises:
- a first memory cell at a first n-type metal-oxide-semiconductor (NMOS) layer of the memory die;
- a second memory cell at a second NMOS layer of the memory die;
- and
- a complimentary metal-oxide semiconductor (CMOS) layer comprising control logic for the memory die;
- and
- a system-on-chip (SOC) communicatively coupled with the package substrate of the electronic device by a conductive element in the memory die.
7 more elements
A microelectronic package comprising:
- a memory die communicatively coupled with a package substrate of the microelectronic package, wherein the memory die comprises:
- a first memory cell at a first n-type metal-oxide-semiconductor (NMOS) layer of the memory die, wherein the first memory cell includes a first dynamic random-access memory (DRAM) cell with an n-type metal-oxide-semiconductor field-effect transistor (MOSFET);
- a second memory cell at a second NMOS layer of the memory die, wherein the second memory cell includes a second DRAM cell with an n-type MOSFET;
- a complimentary metal-oxide semiconductor (CMOS) layer comprising control logic for the memory die;
- and
- a conductive element;
- and
- a system-on-chip (SOC) communicatively coupled with the package substrate of the microelectronic package by the conductive element in the memory die.
5 more elements
Dependencies are inferred from the claim text.