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US 11,901,338 B2Granted
Interwafer connection structure for coupling wafers in a wafer stack
AssigneeXilinx, Inc.
InventorsMyongseob Kim, Henley Liu, Cheang Whang Chang
Life of this patent
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Abstract
An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.
Claims19
An integrated circuit (IC) device comprising:
- a first wafer having a plurality of IC dies formed thereon separated by scribe lanes, the first wafer having a first front side bond pad disposed on an active side and coupled with a first back side bond pad disposed on a back side of the first wafer, and a second front side bond pad disposed on the active side and coupled to a second back side bond pad disposed on the back side of the first wafer;
- a second wafer having a plurality of IC dies formed thereon separated by scribe lanes, the second wafer having a first front side bond pad disposed on an active side and coupled with a first backside bond pad disposed on a back side of the second wafer, and a second front side bond pad disposed on the active side and coupled to a second back side bond pad disposed on the back side of the second wafer;
- a first test key formed in one of the scribe lanes of the first wafer;
- a first hybrid bond interface layer coupling the first wafer to the second wafer, the first hybrid bond interface layer having a first U-turn connection that couples the first back side bond pad to the first test key;
- a second test key disposed in one of the scribe lanes of the second wafer;
- and
- a second hybrid bond interface layer formed on the second wafer, the second hybrid bond interface layer having a second U-turn connection that couples the second back side bond pad of the second wafer to the second test key;
- wherein the second back side bond pad of the first wafer is aligned with and connected to the second front side bond pad of the second wafer through the first hybrid bond interface layer, and
- wherein the second back side bond pad of the second wafer is connected to a back side test key bond pad of the second test key disposed in the second wafer through the second hybrid bond interface layer.
6 more elements
An integrated circuit (IC) device comprising:
- a first wafer having a plurality of IC dies formed thereon separated by scribe lanes, the first wafer having an active side having a first front side bond pad and a back side having a first back side bond pad, the plurality of IC dies formed on the first wafer including a first IC die;
- a second wafer having a plurality of IC dies formed thereon separated by scribe lanes, the second wafer having an active side having a second front side bond pad, and a back side having a second back side bond pad, the plurality of IC dies formed on the second wafer including a second IC die;
- a third wafer having a plurality of IC dies formed thereon separated by scribe lanes, the third wafer having an active side having a third front side bond pad, and a back side having a third back side bond pad, the plurality of IC dies formed on the third wafer including a third IC die that is stacked in alignment with the first and second IC dies;
- a first test key, a second test key, and a third test key formed in one of the scribe lanes of the first wafer;
- a first hybrid bond interface layer coupling the first wafer to the second wafer, the first hybrid bond interface layer having a first U-turn connection that couples the first back side bond pad of the first wafer to the first test key;
- a first test key, a second test key, and a third test key formed in one of the scribe lanes of the second wafer, the test keys of the first wafer vertically aligned with the test keys of the second wafer;
- a second hybrid bond interface layer coupling the second wafer to the third wafer, the second hybrid bond interface layer having a second U-turn connection that couples the second back side bond pad of the second wafer to the second test key of the second wafer, the second U-turn connection not aligned with the first U-turn connection disposed in the first hybrid bond interface layer;
- and
- a first test key, a second test key, and a third test key formed in one of the scribe lanes of the third wafer, the test keys of the third wafer vertically aligned with the test keys of the second wafer;
- and
- a third hybrid bond interface layer formed on the third wafer, the third hybrid bond interface layer having a third U-turn connection that couples the third back side bond pad of the third wafer to the third test key of the third wafer,
- wherein a different one of the test keys of each wafer is coupled to a front side bond pad of the first wafer.
9 more elements
Dependencies are inferred from the claim text.