Semiconductor package

A semiconductor package, comprising:

• a first semiconductor chip having a first front surface and a first rear surface, opposite to the first front surface, including:
• a first substrate layer disposed between the first front surface and the first rear surface,
• a first circuit layer including a first circuit wiring structure and providing the first front surface and disposed on the first substrate layer, and
• a first through via for power penetrating through the first substrate layer and electrically connected to the first circuit wiring structure;
• a second semiconductor chip having a second front surface and a second rear surface, opposite to the second front surface, including:
• a second substrate layer disposed between the second front surface and the second rear surface,
• a second circuit layer including a second circuit wiring structure and providing the second front surface and disposed on the second substrate layer, and
• a second through via for power penetrating through the second substrate layer and electrically connected to the second circuit wiring structure, the second semiconductor chip being disposed on the first semiconductor chip such that the second rear surface faces the first front surface;
• an encapsulation layer covering at least a portion of each of a side surface of the first semiconductor chip and the second rear surface of the second semiconductor chip;
• a third through via for power penetrating through the encapsulation layer and electrically connected to the second through via for power;
• and
• a plurality of connection bumps disposed on a lower surface of the encapsulation layer,
• wherein the first through via for power is electrically connected to a corresponding one of the plurality of connection bumps and the third through via for power is connected to a corresponding one of the plurality of connection bumps, and
• wherein a width of the first semiconductor chip is narrower than a width of the second semiconductor chip.

A semiconductor package, comprising:

• a first semiconductor chip having a first front surface and a first rear surface, opposite to the first front surface, and including:
• a first substrate layer disposed between the first front surface and the first rear surface,
• a first circuit layer including a first circuit structure and providing the first front surface and disposed on the first substrate layer, and
• a first through via for power penetrating through the first substrate layer and electrically connected to the first circuit structure;
• a second semiconductor chip having a second front surface and a second rear surface, opposite to the second front surface, and including:
• a second substrate layer disposed between the second front surface and the second rear surface,
• a second circuit layer including a second circuit structure and providing the second front surface and disposed on the second substrate layer, and
• a second through via for power penetrating through the second substrate layer and electrically connected to the second circuit structure,
• the second semiconductor chip being disposed on the first semiconductor chip such that the second front surface faces the first front surface;
• an encapsulation layer covering at least a portion of each of a side surface of the first semiconductor chip and a side surface of the second semiconductor chip;
• a third through via for power penetrating through the encapsulation layer and adjacent to the side surface of the first semiconductor chip and the side surface of the second semiconductor chip;
• and
• an upper redistribution structure disposed on the encapsulation layer to electrically connect the third through via for power and the second through via for power with each other,
• wherein the first semiconductor chip receives power through the first through via for power, and
• wherein the second semiconductor chip receives power through the third through via for power, the upper redistribution structure, and the second through via for power.