Microelectronic assemblies
AssigneeIntel Corporation
InventorsShawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
Life of this patent
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Abstract
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
Claims20
A microelectronic assembly, comprising:
- a package substrate having an uppermost surface;
- a first die entirely above the uppermost surface of the package substrate, the first die coupled to the package substrate, the first die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall, the first die comprising through silicon vias, the through silicon vias coupled to the package substrate;
- first interconnects entirely above the uppermost surface of the package substrate, the first interconnects laterally spaced apart from the first sidewall of the first die, the first interconnects coupled to the package substrate, and the first interconnects extending an entire vertical length of the first die;
- second interconnects entirely above the uppermost surface of the package substrate, the second interconnects laterally spaced apart from the second sidewall of the first die, the second interconnects coupled to the package substrate, and the second interconnects extending the entire vertical length of the first die;
- a second die vertically over the first interconnects and a first portion of the first die, the second die coupled to the first interconnects and to the first portion of the first die;
- and
- a third die vertically over the second interconnects and a second portion of the first die, the third die coupled to the second interconnects and to the second portion of the first die, the third die laterally spaced apart from the second die.
A method of fabricating a microelectronic assembly, the method comprising:
- coupling a first die to a package substrate, the package substrate having an uppermost surface, the first die entirely above the uppermost surface of the package substrate, and the first die having a first sidewall and a second sidewall, the second sidewall laterally opposite the first sidewall, the first die comprising through silicon vias, the through silicon vias coupled to the package substrate;
- forming first interconnects entirely above the uppermost surface of the package substrate, the first interconnects laterally spaced apart from the first sidewall of the first die, the first interconnects coupled to the package substrate, and the first interconnects extending an entire vertical length of the first die;
- forming second interconnects entirely above the uppermost surface of the package substrate, the second interconnects laterally spaced apart from the second sidewall of the first die, the second interconnects coupled to the package substrate, and the second interconnects extending the entire vertical length of the first die;
- providing a second die vertically over the first interconnects and a first portion of the first die, the second die coupled to the first interconnects and to the first portion of the first die;
- and
- providing a third die vertically over the second interconnects and a second portion of the first die, the third die coupled to the second interconnects and to the second portion of the first die, the third die laterally spaced apart from the second die.
Dependencies are inferred from the claim text.