Three-dimensional (3D) storage device using wafer-to-wafer bonding

A storage device comprising:

• a plurality of nonvolatile memory (NVM) devices each comprising NVM cells;
• and
• a memory controller configured to control the plurality of NVM devices,
• wherein each of the plurality of NVM devices comprises
• a first chip including a peripheral circuit region comprising a first control logic circuit configured to control operation modes of a corresponding NVM device, the peripheral circuit region being on a first surface of a first substrate of the first chip;
• and
• a second chip including three-dimensional (3D) arrays of the NVM cells, the 3D arrays being on a first surface of a second substrate of the second chip, and the second chip being vertically stacked on the first chip so that the first surface of the first substrate is bonded with the first surface of the second substrate, and
• wherein the memory controller comprises a third chip including a control circuit region including circuits configured to set and change operation conditions of each of the plurality of NVM devices, the control circuit region being on a first surface of a third substrate of the third chip, the control circuit region comprises a serializer/deserializer (SERDES) interface configured to transmit and receive data to and from the plurality of NVM devices, and a second control logic circuit associated with the operation conditions of each of the plurality of NVM devices being on the first surface of the third substrate of the third chip.

A storage device comprising:

• a nonvolatile memory (NVM) device comprising NVM cells;
• and
• a memory controller configured to control the NVM device,
• wherein the NVM device comprises:
• a first chip including
• a peripheral circuit region comprising a control logic circuit configured to control operation modes of the NVM device, and
• a control circuit region comprising a memory management unit (MMU) included in the memory controller and configured to set and change operation conditions of the NVM device, the peripheral circuit region and the control circuit region being on a first surface of a first substrate of the first chip;
• and
• a second chip including three-dimensional (3D) arrays of the NVM cells, the 3D arrays are on a first surface of a second substrate of the second chip, and the second chip being vertically stacked on the first chip so that the first surface of the first substrate is bonded with the first surface of the second substrate, and
• wherein the control logic circuit is adjacent to the MMU and is connected to the MMU.