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US 11,901,318 B2Granted
Integrated circuit structure and fabrication method thereof
AssigneeUnited Microelectronics Corp.
InventorsAaron Chen, Chi Ren, Yi Hsin Liu
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Abstract
An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.
Claims16
An integrated circuit structure, comprising:
- a substrate comprising thereon a logic core circuit region and an embedded memory area;
- a copper interconnect structure disposed on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric layer;
- an aluminum pad layer disposed on the dielectric layer, wherein the aluminum pad layer comprises a first pad pattern within the logic core circuit region and a second pad pattern within the embedded memory area;
- a passivation layer covering the first pad pattern within the logic core circuit region and the second pad pattern within the embedded memory area;
- and
- an aluminum shield layer comprising concentric aluminum routing patterns disposed directly on the embedded memory area and between the uppermost copper layer and the aluminum pad layer, wherein the aluminum shield layer has a thickness that is thinner than that of the aluminum pad layer, wherein the first pad pattern and the second pad pattern respectively contact the uppermost copper layer and the aluminum shield layer at different horizontal levels.
3 more elements
A method for forming an integrated circuit structure, comprising:
- providing a substrate comprising thereon a logic core circuit region and an embedded memory area;
- forming a copper interconnect structure on the substrate, wherein the copper interconnect structure comprises an uppermost copper layer covered by a dielectric layer;
- forming an aluminum shield layer comprising concentric aluminum routing patterns on the uppermost copper layer in the embedded memory area;
- and
- forming an aluminum pad layer on the dielectric layer, wherein the aluminum shield layer has a thickness that is thinner than that of the aluminum pad layer, wherein the aluminum pad layer comprises a first pad pattern within the logic core circuit region and a second pad pattern within the embedded memory area;
- and
- forming a passivation layer covering the first pad pattern within the logic core circuit region and the second pad pattern within the embedded memory area.
4 more elements
Dependencies are inferred from the claim text.