Semiconductor memory device including wiring contact plugs

A method of manufacturing a semiconductor memory device, the method comprising:

• preparing a substrate including a cell area and a peripheral area;
• forming a plurality of gate lines on the peripheral area of the substrate;
• forming a plurality of logic bit lines on the plurality of gate lines;
• forming a plurality of lower electrodes on the cell area of the substrate;
• forming a capacitor dielectric layer conformally covering surfaces of the plurality of lower electrodes;
• forming an upper electrode, wherein the forming the upper electrode includes forming a first upper electrode layer filling spaces among the plurality of lower electrodes and covering the capacitor dielectric layer, and forming a second upper electrode layer covering the first upper electrode layer, the first upper electrode layer including a semiconductor material, and the second upper electrode layer including a metallic material;
• forming an etch stop layer covering the upper electrode in the cell area;
• forming a filling insulation layer covering the etch stop layer and the plurality of logic bit lines;
• forming a first wiring contact plug connecting to the second upper electrode layer through the filling insulation layer and the etch stop layer;
• forming a second wiring contact plug connecting to the at least one of the plurality of logic bit lines through the filling insulation layer;
• and
• forming a plurality of wiring lines on the filling insulation layer, at least one of the plurality of wiring lines connecting to the first wiring contact plug and at least another one of the plurality of wiring lines connecting to the second wiring contact plug,
• wherein the second upper electrode layer includes an electrode barrier layer, a main electrode layer including a metallic material, and an interface layer including conductive metal oxide.

A method of manufacturing a semiconductor memory device, the method comprising:

• preparing a substrate including a cell area and a peripheral area;
• forming a plurality of gate lines on the peripheral area of the substrate;
• forming a plurality of logic bit lines on the plurality of gate lines;
• forming a logic capping layer covering upper surfaces of the plurality of logic bit lines;
• forming a plurality of lower electrodes on the cell area of the substrate;
• forming a capacitor dielectric layer covering the plurality of lower electrodes;
• forming an upper electrode, wherein the forming the upper electrode includes forming a first upper electrode layer filling spaces among the plurality of lower electrodes and covering the capacitor dielectric layer, and forming a second upper electrode layer covering the first upper electrode layer, the first upper electrode layer including a semiconductor material, and the second upper electrode layer including a metallic material;
• forming an etch stop layer covering the upper electrode in the cell area;
• forming a filling insulation layer covering the etch stop layer and the logic capping layer;
• forming a first wiring contact plug connecting to the upper electrode through the filling insulation layer and the etch stop layer;
• forming a second wiring contact plug connecting to the at least one of the plurality of logic bit lines through the filling insulation layer and the logic capping layer, a height of the second wiring contact plug being greater than a height of the first wiring contact plug;
• and
• forming a plurality of wiring lines on the filling insulation layer, at least one of the plurality of wiring lines connecting to the first wiring contact plug and at least another one of the plurality of wiring lines connecting to the second wiring contact plug,
• wherein the forming the second upper electrode layer includes forming an electrode barrier layer on the first upper electrode layer, forming a main electrode layer including a metallic material on the electrode barrier layer, and forming an interface layer including a conductive metal oxide on the electrode barrier layer.