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US 11,901,290 B2Granted
Bitcell architecture using buried metal
AssigneeArm Limited
InventorsRajiv Kumar Sisodia, Andy Wangkun Chen
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Abstract
Various implementations described herein are related to a device having multiple transistors that are arranged as a bitcell. The device may include multiple wordlines that are coupled to the multiple transistors. Also, one or more wordlines may be formed with frontside metal, and one or more other wordlines may be formed with buried metal.
Claims20
A device comprising:
- multiple transistors arranged as a bitcell;
- and
- multiple wordlines coupled to the multiple transistors,
- wherein at least one wordline of the wordlines is formed with a frontside metal rail, and
- wherein at least one other wordline of the wordlines is formed with a buried metal rail.
2 more elements
A device comprising:
- a bitcell having a physical layout of first transistors and second transistors arranged in a bitcell structure;
- a first wordline coupled to the first transistors of the bitcell, wherein the first wordline is formed with a frontside metal rail;
- and
- a second wordline coupled to one of the second transistors of the bitcell, wherein the second wordline is formed with a buried metal rail.
1 more element
A device comprising:
- a bitcell having a physical layout of transistors arranged in a bitcell structure, wherein the transistors include first transistors and second transistors;
- a first wordline coupled to the first transistors, wherein the first wordline is formed with a frontside metal rail;
- and
- a second wordline coupled to one of the second transistors, wherein the second wordline is formed with a buried metal rail,
- wherein the transistors include passgate transistors and a read transistor,
- wherein the first wordline includes a write wordline coupled to the passgate transistors, and the write wordline is formed with the frontside metal rail, and
- wherein the second wordline includes a read wordline coupled to the read transistor, and the read wordline is formed with the buried metal rail.
4 more elements
A method comprising:
- fabricating multiple transistors arranged as a bitcell;
- and
- fabricating multiple wordlines coupled to the multiple transistors,
- wherein at least one wordline of the wordlines is formed with a frontside metal rail, and
- wherein at least one other wordline of the wordlines is formed with a buried metal rail.
2 more elements
Dependencies are inferred from the claim text.