Diagonal via pattern and method
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Wei Peng, Chih-Min Hsiao, Ching-Hsu Chang, Jiann-Tyng Tzeng
Life of this patent
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Abstract
A method of generating an integrated circuit (IC) layout diagram includes obtaining a grid of intersecting first and second pluralities of tracks corresponding to adjacent metal layers, determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule, applying a via positioning pattern to the grid whereby via regions are restricted to alternating diagonal grid lines, positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines, and generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.
Claims20
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers;
- determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule;
- applying a via positioning pattern to the grid whereby via region placement is restricted to alternating diagonal grid lines;
- positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines;
- and
- generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers, wherein the first and second pluralities of tracks have respective first and second pitches;
- confirming that one or both of:
- the first and/or second pitch is less than a minimum via spacing rule, or
- a ratio of a greater one of the first or second pitches to a lesser one of the first or second pitches is less than √{square root over (3)};
- applying a via positioning pattern to the grid whereby via region placement is restricted to alternating diagonal grid lines;
- positioning via regions at some or all of the grid intersections of the alternating diagonal grid lines;
- and
- generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.
A method of generating an integrated circuit (IC) layout diagram, the method comprising:
- obtaining a grid comprising grid intersections of first and second pluralities of tracks corresponding to adjacent metal layers;
- determining that first and second pitches of the respective first and second pluralities of tracks conform to a first rule;
- applying a via positioning pattern to the grid by applying a second rule forbidding placing via regions at potential via locations at intersections of the first and second pluralities of tracks, wherein the potential via locations correspond to a first set of diagonal grid lines;
- positioning via regions at some or all of the grid intersections of a second set of diagonal grid lines alternating with the first set of alternating diagonal grid lines;
- and
- generating the IC layout diagram including the via regions positioned along the alternating diagonal grid lines.
Dependencies are inferred from the claim text.