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US 11,901,282 B2Granted
Device isolators
AssigneeTexas Instruments Incorporated
InventorKumar Anurag Shrivastava
Life of this patent
Estimating the term…
Abstract
An integrated semiconductor device having a metallic element formed between a capacitor with and a doped region.
Claims20
An integrated circuit, comprising:
- a substrate;
- a doped region within the substrate;
- first and second metallic elements over the doped region, the first and second metallic elements separated by an oxide region;
- a first metallic contact within the substrate and coupled directly between the first metallic element and the doped region, and a second metallic contact within the substrate and coupled directly between the second metallic element and the doped region;
- and
- a capacitor comprising:
- a third metallic element over the first and second metallic elements, and
- a fourth metallic element over the third metallic element.
5 more elements
An integrated circuit package having a plurality of semiconductor devices, at least one semiconductor device comprising:
- a substrate;
- a doped region within the substrate;
- first and second metallic elements over the doped region, the first and second metallic elements separated by an oxide layer:
- first and second metallic contacts within the substrate, the first metallic contact coupled directly between the first metallic element and the doped region, and the second metallic contact coupled directly between the second metallic element and the doped region;
- and
- a capacitor comprising:
- a bottom electrode over the first and second metallic elements, and
- a top electrode over the bottom electrode.
5 more elements
An integrated circuit package having at least two semiconductor devices, each of the semiconductor devices comprising:
- a substrate;
- a doped region within the substrate;
- first and second metallic elements over the doped region, the first and second metallic elements separated by an oxide region;
- first metallic contacts within the substrate and spaced apart and each having opposite sides and second metallic contacts within the substrate and spaced apart and each having opposite sides, the first metallic contacts contacting the first metallic element on one side and contacting the doped region on the other side, the second metallic contacts contacting the second metallic element on one side and contacting the doped region on the other side;
- and
- a capacitor comprising:
- a first electrode over the first and second metallic elements, and
- a second electrode over the first electrode.
5 more elements
A method comprising:
- providing a substrate;
- forming a doped region within the substrate;
- forming metallic contacts within the substrate on the doped region;
- forming metallic elements on the metallic contacts;
- forming an oxide layer to separate the metallic elements from each other;
- and
- forming a capacitor comprising:
- depositing a first metallic layer over the metallic elements;
- and
- depositing a second metallic layer over the first metallic layer.
7 more elements
A method of making an integrated circuit package having a substrate and a doped region within the substrate, the method comprising:
- forming metallic contacts within the substrate and on the doped region;
- forming metallic elements on the metallic contacts;
- forming an oxide layer to separate the metallic elements from each other;
- and
- forming a capacitor comprising:
- depositing a first metallic layer over the metallic elements;
- and
- depositing a second metallic layer over the first metallic layer.
5 more elements
Dependencies are inferred from the claim text.