High current packages with reduced solder layer count
AssigneeTexas Instruments Incorporated
InventorsYiqi Tang, Liang Wan, William Todd Harrison, Manu Joseph Prakuzhy, Rajen Manicon Murugan
Life of this patent
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Abstract
In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.
Claims27
A semiconductor device, comprising:
- a conductive member including a surface;
- a power supply connection;
- a ground connection;
- a first field effect transistor (FET) including a first surface and a second surface opposite the first surface, wherein:
- a first solder layer disposed on the first surface of the first FET abuts the surface of the conductive member;
- and
- a first plating layer disposed on the second surface of the first FET abuts the power supply connection;
- and
- a second FET having a third surface and a fourth surface opposite the third surface, wherein:
- a second solder layer disposed on the third surface of the second FET abuts the surface of the conductive member;
- and
- a second plating layer disposed on the fourth surface of the second FET abuts the ground connection, wherein the first and second FETs occupy first and second portions of the surface of the conductive member, respectively, the first and second portions not overlapping with each other.
A semiconductor device, comprising:
- a first field effect transistor (FET) including a first surface and a second surface opposite the first surface;
- a first solder layer disposed on the first surface of the first FET;
- a first plating layer disposed on the second surface of the first FET;
- a conductive member abutted to the first plating layer at a first side of the conductive member;
- a second solder layer disposed on a second side of the conductive member opposite the first side of the conductive member;
- a second FET including a first surface and a second surface opposite the first surface, the second solder layer abutted to the first surface of the second FET;
- and
- a second plating layer disposed on the second surface of the second FET.
Dependencies are inferred from the claim text.