Gate structures for semiconductor devices

A semiconductor device, comprising:

• a substrate;
• a fin structure disposed on the substrate;
• a source/drain region disposed on the fin structure;
• nanostructured channel regions disposed on the fin structure and adjacent to the source/drain region;
• and
• a gate structure surrounding nanostructured channel regions, wherein the gate structure comprises:
• an oxide layer surrounding the nanostructured channel regions;
• a gate dielectric layer disposed on the oxide layer;
• a p-type work function metal layer disposed on the gate dielectric layer;
• a silicon-based layer disposed on the p-type work function metal layer;
• and
• a gate metal fill layer.

A semiconductor device, comprising:

• a substrate;
• first and second nanostructured layers disposed on the substrate;
• first and second source/drain regions surrounding the first and second nanostructured layers, respectively;
• and
• first and second gate structures surrounding the first and second nanostructured layers, respectively,
• wherein the first gate structure comprises a first gate dielectric layer, a silicon-based layer, a p-type work function metal layer, and a first gate metal fill layer, and
• wherein the second gate structure comprises a second gate dielectric layer, an n-type work function metal layer, and a second gate metal fill layer.