Integrated circuit device with low threshold voltage
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChung-Liang Cheng, Ziwei Fang
Life of this patent
Estimating the term…
Abstract
A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide.
Claims20
A device, comprising:
- a substrate including a semiconductor material;
- a first gate structure in an n-type region of the substrate;
- and
- a second gate structure in a p-type region of the substrate;
- wherein:
- the first gate structure includes a p-type work function layer deposited over an n-type work function layer, wherein the p-type work function layer includes both ruthenium oxide and unoxidized ruthenium;
- the second gate structure includes the p-type work function layer deposited over the substrate;
- the n-type work function layer includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN.
A device, comprising:
- a first active region and a second active region each disposed over a substrate;
- a first gate structure disposed over the first active region, wherein the first gate structure includes:
- a gate dielectric layer, a first layer disposed over the gate dielectric layer, an n-type work function layer disposed over the first layer, a second layer disposed over the n-type work function layer, and a p-type work function layer disposed over the second layer;
- and
- a second gate structure disposed over the second active region, wherein the second gate structure includes:
- the gate dielectric layer, the first layer disposed over the gate dielectric layer, and the p-type work function layer disposed over the first layer;
- wherein:
- the n-type work function layer includes Ti, Al, Ag, Mn, Zr, TiAl, TiAlC, TaC, TaCN, TaSiN, TaAl, TaAlC, or TiAlN;
- and
- the p-type work function layer includes RuO2 or IrO2.
A device, comprising:
- an n-type transistor that includes:
- a gate dielectric layer, a material layer disposed over the gate dielectric layer, an n-type work function layer disposed over and in physical contact with the material layer, a protective layer disposed over and in physical contact with the n-type work function layer, and a p-type work function layer disposed over and in physical contact with the protective layer;
- and
- a p-type transistor that includes:
- the gate dielectric layer, the material layer disposed over the gate dielectric layer, and the p-type work function layer disposed over and in physical contact with the material layer;
- and
- wherein the p-type work function layer includes a metal oxide material.
Dependencies are inferred from the claim text.