Semiconductor device having cut gate dielectric
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChang-Yun Chang, Bone-Fong Wu, Ming-Chang Wen, Ya-Hsiu Lin
Life of this patent
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Abstract
A device includes a semiconductor fin, a gate structure, gate spacers, and a dielectric feature. The semiconductor fin is over a substrate. The gate structure is over the semiconductor fin and includes a gate dielectric layer over the semiconductor fin and a gate metal covering the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The dielectric feature is over the substrate. The dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers.
Claims20
A device comprising:
- a semiconductor fin over a substrate;
- a gate structure over the semiconductor fin, wherein the gate structure comprises:
- a gate dielectric layer over the semiconductor fin;
- and
- a gate metal covering the gate dielectric layer;
- gate spacers on opposite sides of the gate structure;
- a dielectric feature over the substrate, wherein the dielectric feature is in contact with the gate metal, the gate dielectric layer, and the gate spacers, and an interface between the gate metal and the dielectric feature is substantially aligned with an interface between the dielectric feature and one of the gate spacers;
- and
- an interlayer dielectric (ILD) layer laterally surrounding the gate structure, wherein the dielectric feature comprises:
- a first portion in contact with the gate structure;
- and
- a second portion embedded in the ILD layer, wherein a bottom surface of the first portion is lower than a bottom surface of the second portion.
A device comprising:
- a first semiconductor fin and a second semiconductor fin over a substrate;
- an isolation dielectric over the substrate and surrounding bottom portions of the first semiconductor fin and the second semiconductor fin;
- a gate structure over the first semiconductor fin and the isolation dielectric;
- a dielectric feature between the first semiconductor fin and the second semiconductor fin and directly over the isolation dielectric;
- a helmet layer wrapping the dielectric feature;
- and
- an interlayer dielectric (ILD) layer laterally surrounding the gate structure, wherein the dielectric feature comprises:
- a first portion in contact with the gate structure;
- and
- a second portion embedded in the ILD layer, wherein a bottom surface of the first portion is lower than a bottom surface of the second portion.
A device comprising:
- a semiconductor fin over a substrate and extending in a first direction;
- a gate structure crossing the semiconductor fin and extending in a second direction;
- a source/drain epitaxial structure over the semiconductor fin;
- an interlayer dielectric (ILD) layer covering the source/drain epitaxial structure;
- and
- a dielectric feature over the substrate and extending in the first direction, wherein the dielectric feature comprises:
- a first portion in contact with the gate structure;
- and
- a second portion embedded in the ILD layer, wherein a bottom surface of the first portion is lower than a bottom surface of the second portion.
Dependencies are inferred from the claim text.