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US 11,901,219 B2Granted
Methods of forming semiconductor device structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYi-Wen Pan, You-Lan Li, Chung-Chi Ko
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Abstract
Methods of forming a semiconductor device structure are described. In some embodiments, the method includes forming an interconnect structure over a substrate. The forming the interconnect structure over the semiconductor device structure includes forming a dielectric layer, then performing an annealing process, then forming one or more openings in the dielectric layer, then performing a first ultraviolet (UV) curing process, and then forming conductive features in the one or more openings.
Claims20
A method, comprising:
- forming an interconnect structure over a substrate, comprising:
- forming a dielectric layer;
- then
- performing an annealing process;
- then
- forming one or more openings in the dielectric layer;
- then
- performing a first ultraviolet (UV) curing process;
- then
- forming conductive features in the one or more openings;
- then
- forming a cap layer on the conductive feature, wherein the cap layer comprises a metal and is formed by a plasma enhanced chemical vapor deposition process;
- and then
- performing a second UV curing process after forming the cap layer.
11 more elements
A method, comprising:
- forming one or more semiconductor fins;
- forming an insulating structure to embed the one or more semiconductor fins;
- performing an annealing process;
- recessing the insulating structure to form a shallow trench isolation (STI) region, wherein the recessing the insulating structure is performed by a wet etch process;
- then
- removing electric charge accumulated on the insulating structure as a result of the wet etch process by performing a first ultraviolet (UV) curing process;
- and
- forming one or more sacrificial gate structures.
5 more elements
A method, comprising:
- forming an insulating structure over a substrate;
- performing a first annealing process;
- recessing the insulating structure;
- performing a first ultraviolet (UV) curing process;
- forming source/drain epitaxial features over the substrate;
- forming a gate electrode layer over the substrate;
- forming a dielectric layer over the source/drain epitaxial features and the gate electrode layer;
- performing a second annealing process;
- forming one or more openings in the dielectric layer;
- performing a second UV curing process;
- forming conductive features in the one or more openings,
- forming a cap layer on each of the conductive features by a plasma enhanced chemical vapor deposition process, wherein the cap layer comprises a metal;
- and
- performing a third UV curing process after forming the cap layer.
11 more elements
Dependencies are inferred from the claim text.