# US 11,901,180 B2 · Method of breaking through etch stop layer

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- Number: US 11,901,180 B2
- Document ID: US11901180B2
- Status: Granted
- Kind: B2
- Application number: 17/670,990
- Filed: 2022-02-14
- Published: 2022-06-02
- Granted: 2024-02-13
- Earliest claimed: 2019-12-26
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Shih Wang; Hong-Jie Yang; Chia-Ying Lee; Po-Nan Yeh; U-Ting Chiu; Chun-Neng Lin; Ming-Hsi Yeh; Kuo-Bin Huang
- Web page: https://patentgrep.com/patent/US11901180B2

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10P 76/2041: {Photolithographic processes}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A photo resist layer is used to protect a dielectric layer and conductive elements embedded in the dielectric layer when patterning an etch stop layer underlying the dielectric layer. The photo resist layer may further be used to etch another dielectric layer underlying the etch stop layer, where etching the next dielectric layer exposes a contact, such as a gate contact. The bottom layer can be used to protect the conductive elements embedded in the dielectric layer from a wet etchant used to etch the etch stop layer.

## Claims

### Claim 1

A method comprising:
patterning a resist, the resist overlying a first dielectric layer;
etching the first dielectric layer based on a pattern of the resist to form an opening in the first dielectric layer, the etching stopping on an etch stop layer underlying the first dielectric layer;
while the resist is over the first dielectric layer, extending the opening through the etch stop layer;
after extending the opening through the etch stop layer, etching a second dielectric layer to expose a first metal feature underlying the second dielectric layer, the etched second dielectric layer serving as a mask layer; and
forming a conductive element in the opening in the first dielectric layer, the conductive element electrically coupled to the first metal feature underlying the mask layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming the resist over the first dielectric layer, wherein prior to forming the resist, the first dielectric layer includes a second metal feature, an upper surface of the first dielectric layer aligned with an upper surface of the second metal feature.

### Claim 3 (depends on 2)

The method of claim 2, wherein extending the opening through the etch stop layer uses a wet etch process, and wherein the resist protects the upper surface of the second metal feature from wet etchant while using the wet etch process.

### Claim 4 (depends on 1)

The method of claim 1, wherein the etch stop layer comprises a metal oxide.

### Claim 5 (depends on 4)

The method of claim 4, wherein the metal oxide is aluminum oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein:
extending the opening through the etch stop layer uses a wet etch process.

### Claim 7 (depends on 6)

The method of claim 6, wherein etching the first dielectric layer uses a dry etch process.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first metal feature corresponds to a gate electrode of a transistor.

### Claim 9 (depends on 1)

The method of claim 1, wherein the second dielectric layer corresponds to a gate mask.

### Claim 10

A method comprising:
forming a first contact plug extending through a second interlayer dielectric (ILD), an etch stop, and a gate mask dielectric, the first contact plug contacting a source/drain contact, wherein the first contact plug is free from etch damage at an upper surface of the first contact plug; and
forming a second contact plug extending through the second ILD, the etch stop, and the gate mask dielectric, the second contact plug contacting a gate electrode of a gate structure, the gate structure disposed over a semiconductor fin that extends from a substrate, the gate structure comprising: a gate dielectric on the semiconductor fin, the gate electrode on the gate dielectric, and a gate mask over the gate electrode, wherein a first ILD material laterally surrounds the gate structure, the gate mask dielectric extending continuously over an upper surface of the first ILD material, wherein the etch stop is disposed over the gate mask dielectric.

### Claim 11 (depends on 10)

The method of claim 10, wherein the first contact plug and the second contact plug are formed in different processes.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
after forming the first contact plug, depositing a photomask over the second ILD;
patterning the photomask to form an opening therein;
etching the second ILD through the opening; and
etching the etch stop through the opening.

### Claim 13 (depends on 12)

The method of claim 12, wherein etching the etch stop uses a wet etch technique.

### Claim 14 (depends on 13)

The method of claim 13, wherein etching the second ILD uses a dry etch technique.

### Claim 15 (depends on 12)

The method of claim 12, further comprising:
removing the photomask after etching the etch stop; and
etching the gate mask dielectric through the etched second ILD to expose the gate electrode.

### Claim 16 (depends on 10)

The method of claim 10, wherein the etch stop comprises aluminum oxide, wherein the second ILD comprises a material with a different etch selectivity than the etch stop.

### Claim 17

A method comprising:
forming a mask over a first dielectric layer;
forming a first opening in the mask, the first opening exposing a portion of the first dielectric layer;
etching the first dielectric layer while using the mask as an etch mask to form a second opening in the first dielectric layer, the second opening exposing an etch stop layer;
etching the etch stop layer while using the mask as an etch mask to form a third opening in the etch stop layer; and
forming a first metal feature in the third opening, the first metal feature electrically coupled to a conductive element under the etch stop layer.

### Claim 18 (depends on 17)

The method of claim 17, further comprising:
after etching the etch stop layer, the third opening exposes a second dielectric layer underlying the etch stop layer; and
etching the second dielectric layer while using the mask as an etch mask to form a fourth opening in the second dielectric layer, the first metal feature extending through the fourth opening to contact the conductive element.

### Claim 19 (depends on 17)

The method of claim 17, wherein etching the first dielectric layer comprises a dry etch, wherein etching the etch stop layer comprises a wet etch.

### Claim 20 (depends on 9, 17)

The method of claim 17, the method of claim 9, wherein prior to forming the first opening, the first dielectric layer includes a second metal feature extending through the first dielectric layer.