Multiple differential write clock signals with different phases
AssigneeMicron Technology, Inc.
InventorKeun Soo Song
Life of this patent
Estimating the term…
Abstract
Apparatuses and techniques for operating devices with multiple differential write clock signals having different phases are described. For example, a memory controller (e.g., of a host device) can provide two differential write clock signals to a memory device over an interconnect. The two differential write clock signals may have a phase offset of approximately ninety degrees. Instead of generating its own phase-delayed write clock signals using a component (e.g., a clock divider circuit) that can enter the metastable state, the memory device can use the multiple differential write clocks signals provided by the memory controller to process memory requests.
Claims36
An apparatus comprising:
- at least one memory array;
- and
- an interface coupled to the at least one memory array and configured to be coupled to a memory controller via an interconnect, the interface comprising:
- at least one set of first pins configured to receive, from the memory controller, a first differential write clock signal that passes through the interconnect, the first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees;
- and
- at least one set of second pins configured to receive, from the memory controller, a second differential write clock signal that passes through the interconnect, the second differential write clock signal comprising a third signal having a third phase that differs from the first phase and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees.
A method comprising:
- receiving, from a memory controller, a first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees;
- receiving, from the memory controller, a second differential write clock signal comprising a third signal having a third phase that differs from the first phase and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees;
- and
- processing memory requests using the first differential write clock signal and the second differential write clock signal.
An apparatus comprising:
- an interface configured to be coupled to a memory device via an interconnect;
- and
- clock circuitry coupled to the interface and configured to:
- generate a first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees;
- generate a second differential write clock signal comprising a third signal having a third phase that differs from the first phase by approximately ninety degrees and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees;
- and
- transmit, through the interface, the first differential write clock signal and the second differential write clock signal over the interconnect to the memory device.
A method comprising:
- generating a first differential write clock signal comprising a first signal having a first phase and a second signal having a second phase that differs from the first phase by approximately 180 degrees;
- generating a second differential write clock signal comprising a third signal having a third phase that differs from the first phase and a fourth signal having a fourth phase that differs from the third phase by approximately 180 degrees;
- and
- transmitting the first differential write clock signal and the second differential write clock signal over an interconnect to a memory device.
Dependencies are inferred from the claim text.