Memory system

A memory system comprising:

• a nonvolatile memory;
• and
• a controller electrically connected to the nonvolatile memory and including at least an equalizer circuit and a clock-and-data output circuit,
• wherein the equalizer circuit is configured to:
• receive a first data signal from a host via a serial communication;
• reduce an inter-symbol interference jitter of the first data signal to generate a second data signal;
• and
• output the second data signal, and
• the clock-and-data output circuit is configured to:
• extract a third data signal and a clock signal from the second data signal;
• and
• output the third data signal and the clock signal, and
• wherein the controller is configured to:
• execute, when a link speed with the host is switched from a first link speed to a second link speed, a detection process of detecting predetermined data in the third data signal based on the first data signal received from the host at the second link speed;
• and
• reset a state of the clock-and-data output circuit when the predetermined data is not detected within a predetermined period of time in the detection process.