Apparatuses and methods of power supply control for sense amplifiers

An apparatus, comprising:

• a bank including:
• a first plurality of memory cells;
• a second plurality of memory cells;
• first sense amplifiers coupled to the first plurality of memory cells;
• second sense amplifiers coupled to the second plurality of memory cells;
• a first power control circuit coupled to the first sense amplifiers at a first common power supply node. the first power control circuit configured to receive a plurality of control signals;
• and
• a second power control circuit coupled to the second sense amplifiers at a second common power supply node, the second power control circuit configured to receive the plurality of control signals,
• wherein the first and second power control circuits are configured to have first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals,
• wherein the first drive strength and the second drive strength are different from each other, and
• wherein the first power control circuit and the second power control circuit are configured to have a same drive strength responsive to activation of all the plurality of control signals.

An apparatus comprising:

• a bank including:
• a first plurality of memory cells;
• a second plurality of memory cells;
• first sense amplifiers coupled to the first plurality of memory cells:
• second sense amplifiers coupled to the second plurality of memory cells;
• a first power control circuit coupled to the first sense amplifiers at a first common power supply node, the first power control circuit configured to receive a plurality of control signals;
• and
• a second power control circuit coupled to the second sense amplifiers at a second common power supply node, the second power control circuit configured to receive the plurality of control signals,
• wherein the first and second power control circuits are configured to have first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals,
• wherein the first drive strength and the second drive strength are different from each other, and
• wherein the first common power supply node is coupled to the second common power supply node.

An apparatus comprising:

• a bank including:
• a first plurality of memory cells;
• a second plurality of memory cells:
• first sense amplifiers coupled to the first plurality of memory cells;
• second sense amplifiers coupled to the second pluralit of memory cells;
• a first power control circuit coupled to the first sense amplifiers at a first common power supply node. the first power control circuit configured to receive a plurality of control signals;
• a second power control circuit coupled to the second sense amplifiers at a second common power supply node, the second power control circuit configured to receive the plurality of control signals,
• wherein the first and second power control circuits are configured to have first and second drive strengths respectively responsive to activation of a control signal of the plurality of control signals, and
• wherein the first drive strength and the second drive strength are different from each other;
• a third power control circuit coupled to the first sense amplifiers at a third common power supply node, the first power control circuit configured to receive another plurality of control signals;
• and
• a fourth power control circuit coupled to the second sense amplifiers at a fourth common power supply node, the second power control circuit configured to receive the other plurality of control signals,
• wherein the third and fourth power control circuits are configured to have third and fourth drive strengths respectively responsive to activation of another control signal of the other plurality of control signals, and
• wherein the third drive strength and the fourth drive strength are different from each other.

An apparatus comprising:

• a bank comprising:
• a first plurality of memory cells;
• a second plurality of memory cells;
• first sense amplifiers coupled to the first plurality of memory cells and further coupled to a first common power supply node;
• second sense amplifiers coupled to the second plurality of memory cells and further coupled to a second common power supply node;
• first transistor coupled to the first sense amplifiers at the first common power supply node, the first transistor comprises a first drive strength;
• and
• a second transistor coupled to the second sense amplifiers at the second common power supply node, the second transistor comprises a second drive strength,
• wherein the first and second transistors are configured to receive a control signal,
• wherein the first and second transistors are configured to be activated responsive to the control signal in an active state, and
• wherein the first drive strength and the second drive strength are different from each other.

An apparatus comprising:

• a row decoder including:
• a common power supply circuit configured to provide a common power supply voltage to a common power supply node responsive to a plurality of control signals;
• and
• a bank including:
• a first plurality of memory cells;
• a second plurality of memory cells;
• first sense amplifiers coupled to the first plurality of memory cells and further coupled to the common power supply node;
• second sense amplifiers coupled to the second plurality of memory cells and further coupled to the common power supply node;
• a first power control circuit coupled to the first sense amplifiers at the common power supply node ;
• the first power control circuit configured to receive the plurality of control signals and further configured to provide the common power supply voltage with a first drive strength to the common power supply node responsive to the plurality of control signals;
• and
• a second power control circuit coupled to the second sense amplifiers at the common power supply node, the second power control circuit configured to receive the plurality of control signals and further configured to provide the common power supply voltage with a second drive strength to the common power supply node responsive to the plurality of control signals,
• wherein the first and second drive strengths are different responsive to activation of a first control signal of the plurality of control signals, and
• wherein the common power supply circuit is configured to have a third drive strength and a fourth drive strength different from each other responsive to an activation of the first control signal and an activation of a second control signal after the activation of the first control signal respectively.