Asynchronous multi-plane independent scheme dynamic analog resource sharing in three-dimensional memory devices

A method for performing asynchronous multi-plane independent read operations on a memory device comprising a plurality of memory planes, comprising:

• controlling a first pump set coupled to the plurality of memory planes to supply a first output voltage to a plurality of linear regulators during a steady phase;
• controlling a second pump set coupled to the plurality of memory planes to supply a second output voltage to the plurality of linear regulators during a ramping phase;
• controlling a first linear regulator set in the plurality of linear regulators to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of one of the plurality of memory planes of the memory device;
• controlling a second linear regulator set in the plurality of linear regulators to regulate the first output voltage or the second output voltage to generate a second voltage bias for a second group of word lines of one of the plurality of memory planes of the memory device;
• controlling a second linear regulator subset to regulate the first output voltage to generate the second voltage bias during the steady phase;
• and
• controlling a third linear regulator subset to regulate the second output voltage to generate the second voltage bias during the ramping phase.

A method for performing asynchronous multi-plane independent read operations on a memory device comprising a plurality of memory planes, comprising:

• controlling a first pump set coupled to the plurality of memory planes to supply a first output voltage to a plurality of linear regulators during a steady phase;
• controlling a second pump set coupled to the plurality of memory planes to supply a second output voltage to the plurality of linear regulators during a ramping phase;
• controlling a first linear regulator set in the plurality of linear regulators to regulate the first output voltage or the second output voltage to generate a first voltage bias for a first group of word lines of one of the plurality of memory planes of the memory device;
• controlling the first pump set and/or the second pump set to perform a first ramping operation of a first word line in a first memory plane in response to receiving a first read operation;
• and
• after the first ramping operation of the first word line in the first memory plane is completed, controlling the first pump set and/or the second pump set to perform a second ramping operation of a second word line in a second memory plane in response to receiving a second read operation.