US 11,901,033 B2Granted

Memory device for column repair

AssigneeSamsung Electronics Co., Ltd.

InventorsJooyong Park, Minsu Kim, Daeseok Byeon, Pansuk Kwak

Life of this patent

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Abstract

A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

Claims18

Dependent claims

An operating method of a memory device, the operating method comprising:

receiving an address for memory access from a memory controller;
determining whether a column address in the address is a defect address;
when the column address is not the defect address, accessing first normal memory cells corresponding to the column address;
and
when the column address is the defect address, accessing first redundant memory cells corresponding to a repair address,
wherein the memory device includes:
first page buffers arranged collinearly in a first direction and connected to normal memory cells through first bit lines extending in the first direction, the first page buffers divided into a first plurality of repair groups including a first repair group and a second repair group, the first normal memory cells corresponding to the first repair group or the second repair group, and
second page buffers arranged collinearly in the first direction and connected to redundant memory cells through second bit lines extending in the first direction, the second page buffers divided into a second plurality of repair groups including a third repair group and a fourth repair group, the first redundant memory cells corresponding to the third repair group or the fourth repair group,
wherein a width of a region including the first bit lines is the same as a width of a gate in a transistor in a second direction, the transistor included in each of the first page buffers, and
transistors included in each of the first page buffers are collinear in the first direction.

7 more elements

An operating method of a memory device including first page buffers connected to a first bit line group, second page buffers connected to a second bit line group, third page buffers connected to a third bit line group, and fourth page buffers connected to a fourth bit line group, the operating method comprising:

receiving an address for memory access from a memory controller;
determining whether a column address in the address is a defect address;
when the column address is not the defect address, accessing first normal memory cells corresponding to the column address, the first normal memory cells connected to the first bit line group or the second bit line group;
when the column address is the defect address, accessing first redundant memory cells corresponding to a repair address, the first redundant memory cells connected to the third bit line group or the fourth bit line group;
and
outputting as a decoder output signal, first data received from the first page buffers through a first wired OR line, second data received from the second page buffers through a second wired OR line, third data received from the third page buffers through a third wired OR line, and fourth data received from the fourth page buffers through a fourth wired OR line, the outputting according to column repair information,
wherein the first and second page buffers are connected to normal memory cells and collinear in a first direction,
the third and fourth page buffers are connected to redundant memory cells and collinear in the first direction,
a first width of a region including the first bit line group is the same as a width of a first gate in a first transistor of a second direction, the first transistor included in each of the first page buffers,
a second width of a second region including the second bit line group is the same as a width of a second gate of a second transistor in the second direction, the second transistor included in each of the second page buffers, and
the first transistor in the first page buffers and the second transistor included in the second page buffers are collinear in the first direction.

8 more elements

receiving an address for memory access from a memory controller;
determining whether a column address in the address is a defect address;
when the column address is not the defect address, outputting first data received from the first page buffers according to first column repair information in response to a first selection signal corresponding to the first bit line group being in an enabled state, and outputting second data received from the second page buffers according to second column repair information in response to a second selection signal corresponding to the second bit line group being in the enabled state;
and
when the column address is the defect address, outputting third data received from the third page buffers according to third column repair information in response to a third selection signal corresponding to the third bit line group being in the enabled state, and outputting fourth data received from the fourth page buffers according to fourth column repair information in response to a fourth selection signal corresponding to the fourth bit line group being in the enabled state,
wherein the first and second page buffers are connected to normal memory cells and collinear in a first direction,
the third and fourth page buffers are connected to redundant memory cells and collinear in the first direction,
a first width of a region including the first bit line group is the same as a width of a first gate in a first transistor of a second direction, the first transistor included in each of the first page buffers,
a second width of a second region including the second bit line group is the same as a width of a second gate of a second transistor in the second direction, the second transistor included in each of the second page buffers, and
the first transistor in the first page buffers and the second transistor included in the second page buffers are collinear in the first direction.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/149,302Filed 3 Jan 2023 · continuation
Priority: KR 10-2020-012754129 Sep 2020
Published: US 2023/0154559 A118 May 2023
Granted: 13 Feb 2024
Term ends: Not estimatedThe source records don’t support an estimate.

Classification35 codes

G11C 29/81
With improved layout: using a hierarchical redundancy scheme
G11C 29/838
Using programmable devices: with substitution of defective spares
G06F 11/2094
Where persistent mass storage functionality or persistent mass storage control functionality is redundant: redundant storage or storage space
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series

Family

Application17/245,568Parent of this continuation · filed 30 Apr 2021
US 2023/0154559 A1Pre-grant publication · published 18 May 2023
US 11,574,700 B2Parent of this continuation
US 2022/0100622 A1Published application
US 11,901,033 B2This patent

From the US filing history. Foreign family members aren’t listed.