Memory device performing repair operation
AssigneeSK hynix Inc.
InventorsYong Sun Kim, Mi Hyun Hwang
Life of this patent
Estimating the term…
Abstract
A memory device includes a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal. The memory device also includes a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag.
Claims17
A memory device comprising:
- a fail test circuit configured to generate a fail flag indicating whether a failure was detected in a column line, on the basis of internal data outputted from the column line selected according to a column address, when performing a test, and control the fail flag to indicate that the failure was detected in the column line, on the basis of a fail control signal;
- a repair information generation circuit configured to generate, from the column address, a repair column address for repairing the column line, on the basis of the fail flag, and
- wherein the fall test circuit configured to generate the fall flag when the test is performed basis of a test mode signal generated from a command address.
A memory device comprising:
- a bank fail test circuit configured to generate a first fail bank flag indicating whether a failure was detected in a first memory bank, on the basis of first internal data outputted from a column line of the first memory bank, and control the first fail bank flag to indicate that a failure was detected in the first memory bank, on the basis of a first fail control signal, when performing a test;
- an active row region information output circuit configured to output first bank active row region information as active row region information for repairing the column line, on the basis of the first fail bank flag, the first bank active row region information being generated when an active operation is performed in the first memory bank, and
- wherein the bank fall test circuit configured to generate the first fall bank flag when the test is performed basis of a test mode signal generated from a command address.
Dependencies are inferred from the claim text.