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US 11,901,026 B2Granted
Partial refresh
AssigneeNeuroBlade Ltd.
InventorsElad Sity, Eliad Hillel
Life of this patent
Estimating the term…
Abstract
A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.
Claims20
A memory chip comprising:
- a plurality of memory banks;
- a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks,
- a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information, and
- a sense amplifier configured to access the one or more segments,
- wherein the data storage comprises at least one bit register associated with the one or more segments, wherein a state of the at least one bit register is configured to be changed in response to the one or more segments being accessed,
- wherein the refresh controller is configured to skip a refresh of the one or more segments based on the state of the at least one bit register,
- wherein the sense amplifier is configured to communicate with the refresh controller configured to update the state of the at least one bit register.
4 more elements
A method for refreshing memory banks on a memory chip, the method comprising:
- updating a state of at least one bit register by a sense amplifier configured to access one or more segments of a plurality of the memory banks on the memory chip,
- the at least one bit register associated with one or more of the segments,
- wherein a state of the at least one bit register is configured to be changed in response to the one or more segments being accessed;
- accessing a data storage including the at least one bit register containing information indicative of access operations for one or more segments of a plurality of memory banks included on the memory chip;
- and
- performing a refresh operation, with a refresh controller, of the one or more segments based, at least in part, on the stored information indicative of access operations;
- wherein the refresh controller is configured to skip a refresh of the one or more segments based on the state of the at least one bit register.
4 more elements
Dependencies are inferred from the claim text.