Semiconductor memory device and method of operating semiconductor memory device

A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each including a plurality of volatile memory cells, the method comprising:

• storing a portion of access addresses by using first repair controllers, which are unused for storing defective addresses, among from a plurality of repair controllers, each including a defective address storage;
• generating, by at least one of the first repair controllers, a matching signal based on a comparison of a target access address and stored access addresses therein;
• providing, by a connection logic, the matching signal to a corresponding counter in a row hammer management circuit;
• storing, by the row hammer management circuit, a counting value of the corresponding counter in an access storage;
• determining, by the row hammer management circuit, a hammer address based on comparing the counting value with a reference number;
• and
• performing, by a refresh control circuit, a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cell rows, each including a plurality of volatile memory cells;
• a row hammer management circuit configured to:
• count each of access addresses associated with access to each of the plurality of memory cell rows to store counting values therein;
• and
• determine a hammer address associated with at least one of the plurality of memory cell rows, which is intensively accessed, based on the counting values;
• a refresh control circuit configured to perform a refresh operation on the plurality of memory cell rows and a hammer refresh operation on victim memory cell rows which are physically adjacent to a memory cell row corresponding to the hammer address;
• a repair control circuit including a plurality of repair controllers, each of the plurality of repair controllers configured to store a defective address storage, the repair control circuit configured to repair a defective memory cell row among from the plurality of memory cell rows;
• and
• a connection logic configured to connect the row hammer management circuit to first repair controllers, the first repair controllers being a portion of the plurality of repair controllers unused for storing defective addresses,
• wherein the row hammer management circuit is configured to manage row hammers of the plurality of memory cell rows by using the first repair controllers as a storage resource to store a portion of the access addresses.