US 11,901,023 B2 · Architecture and method for NAND memory operation

Abstract

In a method for reading a memory device including a first memory cell string, in a pre-verify stage, a first verify voltage is applied on a gate terminal of a selected memory cell of the first memory cell string, where the selected memory cell is programmed and arranged between a first adjacent memory cell and a second adjacent memory cell. A first bias voltage is applied on a gate terminal of at least one memory cell of the first memory cell string that is not programmed. In a verify stage, a second verify voltage is applied on the gate terminal of the selected memory cell of the first memory cell string. A second bias voltage is applied on the gate terminal of the at least one memory cell of the first memory cell string that is not programmed, where the second bias voltage is smaller than the first bias voltage.

Claims20

Dependent claims

A memory device, comprising:

a memory cell string that includes memory cells (MCs) that are connected in series;
word line layers coupled respectively with the MCs, the word line layers including a selected word line layer coupled to one of the MCs that is selected for a verify or read operation, and an unselected word line layer coupled to one of the MCs that is not selected for the verify or read operation;
and
processing circuitry configured to:
apply, in a pre-pulse stage, a first verify/read bias voltage on the selected word line layer;
apply, in the pre-pulse stage, a first bias voltage on the unselected word line layer;
apply, in a verify/read stage, a second verify/read voltage on the selected word line layer;
and
apply, in the verify/read stage, a second bias voltage on the unselected word line layer, wherein the second bias voltage is smaller than the first bias voltage.

6 more elements

A method of operating a memory device comprising a memory cell string that includes memory cells (MCs) that are connected in series, and word line layers coupled respectively with the MCs, the word line layers including a selected word line layer coupled to one of the MCs that is selected for a verify or read operation, and an unselected word line layer coupled to one of the MCs that is not selected for the verify or read operation, the method comprising:

applying, in a pre-pulse stage, a first verify/read bias voltage on the selected word line layer;
applying, in the pre-pulse stage, a first bias voltage on the unselected word line layer;
applying, in a verify/read stage, a second verify/read voltage on the selected word line layer;
and
applying, in the verify/read stage, a second bias voltage on the unselected word line layer, wherein the second bias voltage is smaller than the first bias voltage.

2 more elements

Dependencies are inferred from the claim text.

Architecture and method for NAND memory operation

Life of this patent

Architecture and method for NAND memory operation

Life of this patent

Abstract

Claims20