Non-volatile memory device and method for programming the same using multiple program operations under different conditions

A method for programming at least one selected memory cell of a plurality of memory cells included in a non-volatile memory device, each of the plurality of memory cells being connected to a word line of a plurality of word lines and a bit line of a plurality of bit lines, the non-volatile memory device including a memory cell region including a first metal pad and the plurality of memory cells, the non-volatile memory device further including a peripheral region including a second metal pad and a voltage generator the peripheral region connected to the plurality of memory cells through the first metal pad and the second metal pad, the method comprising:

• performing a first program operation based on a first condition, the first program operation including:
• generating a first bit line voltage, a first program voltage, a first adjacent voltage, and a first pass voltage by the voltage generator, wherein voltage levels and voltage application times of the first bit line voltage, the first program voltage, the first adjacent voltage, and the first pass voltage correspond to the first condition;
• and
• providing the first bit line voltage to a selected bit line connected to the at least one selected memory cell, providing the first program voltage to a selected word line connected to the at least one selected memory cell, providing the first adjacent voltage to word lines immediately adjacent to the selected word line, and providing the first pass voltage to word lines not immediately adjacent to the selected word line;
• performing a first verify operation based on the first condition, including generating a first verify voltage by the voltage generator and providing the first verify voltage to the selected word line;
• performing a second program operation based on a second condition, the second program operation including:
• generating a second bit line voltage, a second program voltage, a second adjacent voltage, and a second pass voltage by the voltage generator, wherein voltage levels and voltage application times of the second bit line voltage, the second program voltage, the second adjacent voltage, and the second pass voltage correspond to the second condition;
• and
• providing the second bit line voltage to the selected bit line, providing the second program voltage to the selected word line, providing the second adjacent voltage to the word lines immediately adjacent to the selected word line, and providing the second pass voltage to the word lines not immediately adjacent to the selected word line;
• and
• performing a second verify operation based on the second condition, including generating a second verify voltage by the voltage generator and providing the second verify voltage to the selected word line,
• wherein the first condition is different from the second condition, and wherein the at least one selected memory cell is formed perpendicularly to a substrate included in the non-volatile memory device.

A non-volatile memory device comprising:

• a substrate;
• a memory cell region comprising a first metal pad, a memory cell array comprising a plurality of cell strings comprising a plurality of memory cells formed perpendicularly to the substrate, a plurality of string select lines respectively connected to the plurality of memory cells, and a plurality of word lines respectively connected to the plurality of memory cells;
• and
• a peripheral circuit region comprising:
• a second metal pad;
• a control logic configured to control a first program operation and a second program operation for the memory cell array by providing a control signal and an address signal;
• a voltage generator configured to generate at least one voltage based on the control signal;
• a row decoder configured to provide the at least one voltage to the memory cell array during the first program operation and the second program operation via at least one of the plurality of string select lines and the plurality of word lines based on the address signal;
• and
• a program logic circuit configured to adjust at least one of a voltage level and an application time of the at least one voltage for the second program operation based on a result of the first program operation,
• wherein the peripheral region is connected to the memory cell region through the first metal pad and the second metal pad.