Semiconductor storage device comprising a control circuit for changing a rate of increase of a voltage applied to non-selected word lines

Abstract

[Problem] To provide a semiconductor storage device capable of reducing the load on a controller. [Solution] According to one embodiment, a semiconductor storage device 2 includes a memory cell array 110 including a plurality of memory cell transistors MT, a plurality of word lines WL connected to gates of the respective memory cell arrays 110, a voltage generation circuit 43 generating a voltage applied to each of the word lines WL, and a sequencer 41 controlling an operation of the memory cell array 110. The sequencer 41 repeats a loop including a program operation and a verify operation multiple times in a write operation. The sequencer 41 controls an operation of the voltage generation circuit 43 so that a rate increase in a voltage applied to a non-selected word line in the verify operation of a last loop is smaller than the rate increase in the voltage applied to the non-selected word line in the verify operation of a first loop.

Dependencies are inferred from the claim text.